DS92LV2421_11 Datasheet, PDF (8/40 Pages) National Semiconductor (TI) – 10 to 75 MHz, 24-bit Channel Link II Serializer and Deserializer

Pin Name
Pin #
I/O, Type
NC
1, 15, 16,
30, 31, 45,
46, 60
Channel-Link II — CML Serial Interface
RIN+
49
I, CML
RIN-
50
I, CML
CMF
51
I, Analog
ROUT+
52
O, CML
ROUT-
53
O, CML
Power and Ground (see NOTE below)
VDDL
29
Power
VDDIR
48
Power
VDDR
43, 55
Power
VDDSC
4, 58
Power
VDDPR
57
Power
VDDCMLO
54
Power
VDDIO
13, 24, 38 Power
GND
DAP
Ground
Description
Not Connected
Leave pin open (float)
True Input. The input must be AC Coupled with a 0.1 μF capacitor.
Inverting Input. The input must be AC Coupled with a 0.1 μF capacitor.
Common-Mode Filter
VCM center-tap is a virtual ground which may be ac-coupled to ground to increase receiver
common mode noise immunity. Recommended value is 4.7 μF or higher.
True Output — Receive Signal after the Equalizer
NC if not used or connect to test point for monitor. Requires I2C control to enable.
Inverting Output — Receive Signal after the Equalizer
NC if not used or connect to test point for monitor. Requires I2C control to enable.
Logic Power, 1.8 V ±5%
Input Power, 1.8 V ±5%
RX High Speed Logic Power, 1.8 V ±5%
SSCG Power, 1.8 V ±5%
PLL Power, 1.8 V ±5%
RX High Speed Logic Power, 1.8 V ±5%
LVCMOS I/O Power, 1.8 V ±5% OR 3.3 V ±10% (V_DDIO)
DAP is the large metal contact at the bottom side, located at the center of the LLP package.
Connected to the ground plane (GND) with at least 9 vias.
NOTE: 1 = HIGH, 0 = LOW
The VDD (V_DDn and V_DDIO) supply ramp should be faster than 1.5 ms with a monotonic rise. If slower then 1.5 ms then a capacitor
on the PDB pin is needed to ensure PDB arrives after all the VDD have settled to the recommended operating voltage.
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