DS92LV2421_11 Datasheet, PDF (30/40 Pages) National Semiconductor (TI) – 10 to 75 MHz, 24-bit Channel Link II Serializer and Deserializer

FIGURE 27. BIST Waveforms
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Optional Serial Bus Control
The Ser and Des may also be configured by the use of a serial
control bus that is I2C protocol compatible. By default, the I2C
reg_0x00'h is set to 00'h and all configuration is set by control/
strap pins. A write of 01'h to reg_0x00'h will enable/allow con-
figuration by registers; this will override the control/strap pins.
Multiple devices may share the serial control bus since mul-
tiple addresses are supported. See Figure 28.
The serial bus is comprised of three pins. The SCL is a Serial
Bus Clock Input. The SDA is the Serial Bus Data Input / Out-
put signal. Both SCL and SDA signals require an external pull
up resistor to V_DDIO. For most applications a 4.7 k pull up re-
sistor to V_DDIO may be used. The resistor value may be
adjusted for capacitive loading and data rate requirements.
The signals are either pulled High, or driven Low.
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FIGURE 28. Serial Control Bus Connection
The third pin is the ID[X] pin. This pin sets one of five possible
device addresses. Three different connections are possible.
The pin may be tied to ground. The pin may be pulled to
V_DD (1.8V, NOT V_DDIO)) with a 10 kΩ resistor. Or a 10 kΩ pull
up resistor (to V_DD 1.8V, NOT V_DDIO)) and a pull down resistor
of the recommended value to set other three possible ad-
dresses may be used. See Table 11 for the Ser and Table
12 for the Des.
The Serial Bus protocol is controlled by START, START-Re-
peated, and STOP phases. A START occurs when SCL
transitions Low while SDA is High. A STOP occurs when SDA
transition High while SCL is also HIGH. See Figure 29
FIGURE 29. START and STOP Conditions
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To communicate with a remote device, the host controller
(master) sends the slave address and listens for a response
from the slave. This response is referred to as an acknowl-
edge bit (ACK). If a slave on the bus is addressed correctly,
it Acknowledges (ACKs) the master by driving the SDA bus
low. If the address doesn't match a device's slave address, it
Not-acknowledges (NACKs) the master by letting SDA be
pulled High. ACKs also occur on the bus when data is being
transmitted. When the master is writing data, the slave ACKs
after every data byte is successfully received. When the mas-
ter is reading data, the master ACKs after every data byte is
received to let the slave know it wants to receive another data
byte. When the master wants to stop reading, it NACKs after
the last data byte and creates a stop condition on the bus. All
communication on the bus begins with either a Start condition
or a Repeated Start condition. All communication on the bus
ends with a Stop condition. A READ is shown in Figure 30
and a WRITE is shown in Figure 31.
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