DS92LV2421_11 Datasheet, PDF (3/40 Pages) National Semiconductor (TI) – 10 to 75 MHz, 24-bit Channel Link II Serializer and Deserializer

DS92LV2421 Pin Diagram
Serializer - DS92LV2421 — Top View
30110119
DS92LV2421 Serializer Pin Descriptions
Pin Name
Pin #
I/O, Type Description
LVCMOS Parallel Interface
DI[7:0]
34, 33, 32, 29, I, LVCMOS Parallel Interface Data Input Pins
28, 27, 26, 25 w/ pull-down For 8–bit RED Display: DI7 = R7 – MSB, DI0 = R0 – LSB.
DI[15:8]
42, 41, 40, 39, I, LVCMOS Parallel Interface Data Input Pins
38, 37, 36, 35 w/ pull-down For 8–bit GREEN Display: DI15 = G7 – MSB, DI8 = G0 – LSB.
DI[23:16] 2, 1, 48, 47, I, LVCMOS Parallel Interface Data Input Pins
46, 45, 44, 43 w/ pull-down For 8–bit BLUE Display: DI23 = B7 – MSB, DI16 = B0 – LSB.
CI1
5
I, LVCMOS Control Signal Input
w/ pull-down For Display/Video Application: CI1 = Data Enable Input
Control signal pulse width must be 3 clocks or longer to be transmitted when the Control
Signal Filter is enabled (CONFIG[1:0] = 01). There is no restriction on the minimum
transition pulse when the Control Signal Filter is disabled (CONFIG[1:0] = 00). The signal
is limited to 2 transitions per 130 clocks regardless of the Control Signal Filter setting.
CI2
3
I, LVCMOS Control Signal Input
w/ pull-down For Display/Video Application: CI2 = Horizontal Sync Input
Control signal pulse width must be 3 clocks or longer to be transmitted when the Control
Signal Filter is enabled (CONFIG[1:0] = 01). There is no restriction on the minimum
transition pulse when the Control Signal Filter is disabled (CONFIG[1:0] = 00). The signal
is limited to 2 transitions per 130 clocks regardless of the Control Signal Filter setting.
CI3
4
I, LVCMOS Control Signal Input
w/ pull-down For Display/Video Application: CI3 = Vertical Sync Input
CI3 is limited to 1 transition per 130 clock cycles. Thus, the minimum pulse width allowed
is 130 clock cycle wide.
3
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