DS92LV2421_11 Datasheet, PDF (4/40 Pages) National Semiconductor (TI) – 10 to 75 MHz, 24-bit Channel Link II Serializer and Deserializer

Pin Name
Pin #
I/O, Type Description
CLKIN
10
I, LVCMOS Clock Input
w/ pull-down Latch/data strobe edge set by RFB pin.
Control and Configuration
PDB
21
I, LVCMOS Power-down Mode Input
w/ pull-down PDB = 1, Ser is enabled (normal operation).
Refer to ”Power Up Requirements and PDB Pin” in the Applications Information Section.
PDB = 0, Ser is powered down. When the Ser is in the power-down state, the driver outputs
(DOUT+/-) are both logic high, the PLL is shutdown, IDD is minimized. Control Registers
are RESET.
VODSEL
24
I, LVCMOS Differential Driver Output Voltage Select (This is can also be control by I2C register.)
w/ pull-down VODSEL = 1, LVDS VOD is ±420 mV, 840 mVp-p (typ) — long cable / De-Emph apps
VODSEL = 0, LVDS VOD is ±280 mV, 560 mVp-p (typ) — short cable (no De-emph), low
power mode.
De-Emph
23
I, Analog De-Emphasis Control (This can also be controlled by I2C register access.)
w/ pull-up De-Emph = open (float) - disabled
To enable De-emphasis, tie a resistor from this pin to GND or control via register.
See Table 4.
RFB
11
I, LVCMOS Clock Input Latch/Data Strobe Edge Select (This can also be controlled by I2C register
w/ pull-down access.)
RFB = 1, parallel interface data and control signals are latched on the rising clock edge.
RFB = 0, parallel interface data and control signals are latched on the falling clock edge.
CONFIG
[1:0]
13, 12
I, LVCMOS 00: Control Signal Filter DISABLED
w/ pull-down 01: Control Signal Filter ENABLED
10: Reverse compatibility mode to interface with the DS90UR124 or DS99R124Q
11: Reverse compatibility mode to interface with the DS90C124
ID[x]
6
I, Analog I2C Serial Control Bus Device ID Address Select — Optional
Resistor to Ground and 10 kΩ pull-up to 1.8V rail. See Table 11.
SCL
SDA
BISTEN
8
I, LVCMOS I2C Serial Control Bus Clock Input - Optional
SCL requires an external pull-up resistor to V_DDIO.
9
I/O, LVCMOS I2C Serial Control Bus Data Input / Output - Optional
Open Drain SDA requires an external pull-up resistor V_DDIO.
31
I, LVCMOS BIST Mode — Optional
w/ pull-down BISTEN = 0, BIST is disabled (normal operation)
BISTEN = 1, BIST is enabled
RES[2:0]
18, 16, 15 I, LVCMOS Reserved - tie LOW
w/ pull-down
Channel-Link II — CML Serial Interface
DOUT+
20
O, CML Non–Inverting Output.
The output must be AC Coupled with a 0.1 µF capacitor.
DOUT-
19
O, CML Inverting Output.
The output must be AC Coupled with a 0.1 µF capacitor.
Power and Ground (see NOTE below)
VDDL
7
Power Logic Power, 1.8 V ±5%
VDDP
14
Power PLL Power, 1.8 V ±5%
VDDHS
17
Power TX High Speed Logic Power, 1.8 V ±5%
VDDTX
22
Power Output Driver Power, 1.8 V ±5%
VDDIO
30
Power LVCMOS I/O Power, 1.8 V ±5% OR 3.3 V ±10%
GND
DAP
Ground
DAP is the large metal contact at the bottom side, located at the center of the LLP
package. Connect to the ground plane (GND) with at least 9 vias.
NOTE: 1= HIGH, 0 L= LOW
The VDD (V_DDn and V_DDIO) supply ramp should be faster than 1.5 ms with a monotonic rise. If slower then 1.5 ms then a capacitor
on the PDB pin is needed to ensure PDB arrives after all the VDD have settled to the recommended operating voltage.
www.national.com
4