DS92LV2421_11 Datasheet, PDF (25/40 Pages) National Semiconductor (TI) – 10 to 75 MHz, 24-bit Channel Link II Serializer and Deserializer

the embedded clock bits are not present. When the serial
stream starts again, the Des will then lock to the incoming
signal and recover the data. Note – in STOP STREAM
SLEEP, the optional Serial Bus Control Registers values are
RETAINED.
Des — CLOCK-DATA RECOVERY STATUS FLAG (LOCK)
and OUTPUT STATE SELECT (OSS_SEL)
When PDB is driven HIGH, the CDR PLL begins locking to
the serial input and LOCK goes from TRI-STATE to LOW
(depending on the value of the OSS_SEL setting). After the
DS92LV2422 completes its lock sequence to the input serial
data, the LOCK output is driven HIGH, indicating valid data
and clock recovered from the serial input is available on the
parallel bus and clock outputs. The CLKOUT output is held at
its current state at the change from OSC_CLK (if this is en-
abled via OSC_SEL) to the recovered clock (or vice versa).
If there is a loss of clock from the input serial stream, LOCK
is driven Low and the state of the outputs are based on the
OSS_SEL setting (STRAP PIN configuration or register).
Des — Oscillator Output — Optional
The Des provides an optional clock output when the input
clock (serial stream) has been lost. This is based on an inter-
nal oscillator. The frequency of the oscillator may be selected.
This feature may be controlled by the external pin or by reg-
ister. See Table 9 and Table 10.
TABLE 8. OSS_SEL and PDB Configuration — Des Outputs
Serial
Input
X
X
Static
Static
Active
INPUTS
PDB
L
L
H
H
H
OSS_SEL
L
H
L
H
X
CLKOUT
Z
L
Z
L
Active
OUTPUTS
DO[23:0], CO1,
CO2, CO3
LOCK
Z
Z
L
L
Z
L
L
L
Active
H
PASS
Z
H
H
H
H
TABLE 9. OSC (Oscillator) Mode — Des Output
INPUTS
Embedded CLK
CLKOUT
NOTE *
OSC
Output
Present
Toggling
* NOTE — Absent and OSC_SEL ≠ 000
OUTPUTS
DO[23:0]/CO1/CO2/CO3
L
Active
LOCK
L
H
PASS
H
H
FIGURE 21. Des Outputs with Output State Select Low (OSS_SEL = L)
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