DS50PCI401 Datasheet, PDF (8/32 Pages) National Semiconductor (TI) – 2.5 Gbps / 5.0 Gbps 4 Lane PCI Express Transceiver with Equalization and De-Emphasis

USING RXDETA/B IN A PCIe ENVIRONMENT
In order for upstream and downstream PCIe subsystems to
communicate in a cabling environment, the PCIe specification
includes several auxiliary or sideband signals to manage sys-
tem-level functionality or implementation. Similar methods
are used in backplane applications, but the exact implemen-
tation falls outside the PCIe standard. Initial communication
from the downstream subsystem to the upstream subsystem
is done with the CPRSNT# auxiliary signal. The CPRSNT#
signal is asserted Low by the downstream componentry after
the "Power Good" condition has been established. This
mechanism allows for the upstream subsystem to determine
whether the power is good within the downstream subsystem,
enable the reference clock, and initiate the Link Training Se-
quence.
FIGURE 2. Typical PCIe System Timing
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The signals shown in the graphic could be easily replicated
within the downstream subsystem and used to control the
RXDETA/B inputs on the DS50PCI401. Often an onboard mi-
crocontroller will be used to handle events like power-up,
power-down, power saving modes, and hot insertion. The mi-
crocontroller would use the same information to determine
when to enable and disable the DS50PCI401 input termina-
tion. In applications that require SMBus control, the micro-
controller could also delay any response to the upstream
subsystem to allow sufficient time to correctly program the
DS50PCI401 and other devices on the board.
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