DS50PCI401 Datasheet, PDF (13/32 Pages) National Semiconductor (TI) – 2.5 Gbps / 5.0 Gbps 4 Lane PCI Express Transceiver with Equalization and De-Emphasis

Note 6: PCIe 2.0 transmit jitter specifications - actual device jitter is much less. Actual device Rj and Dj has been characterized and specified with test loads
outlined in the EQUALIZATION and DE-EMPHASIS sections of the Electrical Characteristics table.
Note 7: Guaranteed by device characterization
Note 8: Propagation Delay measurements for Part to Part skew are all based on devices operating under indentical temperature and supply voltage conditions.
Note 9: Propagation Delay measurements will change slightly based on the level of EQ selected. EQ Bypass will result in the shortest propagation delays.
Note 10: Residual DJ measurements subtract out deterministic jitter present at the generator outputs. For 2.5 Gbps generator Dj = 0.0275 UI and for 5.0 Gbps
generator Dj = 0.035 UI.
Note 11: Measured with a repeating K28.5 pattern at a data rate of 2.5 Gbps and 5.0 Gbps.
Note 12: Measured with DEM Select pins configured for 1000mV VOD, see De-emphasis table.
Note 13: Measured at default SD_TH settings
Note 14: Input edge rate for LVCMOS/FLOAT inputs must be 50ns minimum from 10-90%.
Note 15: Measured at package pins of receiver. Less than 40mV is IDLE, greater than 175mV is ACTIVE. SD_TH pin connected with resistor to GND overrides
this default setting.
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