DS50PCI401 Datasheet, PDF (11/32 Pages) National Semiconductor (TI) – 2.5 Gbps / 5.0 Gbps 4 Lane PCI Express Transceiver with Equalization and De-Emphasis

Symbol
V_{TX-CM-DC- LINE-DELTA}
T_{TX-IDLE-SET-TO -IDLE}
T_{TX-IDLE-TO -DIFF-DATA}
T_PDEQ
T_PD
T_LSK
T_PPSK
Parameter
Conditions
Absolute Delta of DC
Common Mode
Voltage between Tx+
and Tx-
Max time to transition to VIN = 800 mVp-p, 5 Gbps,
valid diff signaling after Figure 5
leaving Electrical Idle
Max time to transition to VIN = 800 mVp-p, 5 Gbps,
valid diff signaling after Figure 5
leaving Electrical Idle
Differential
Propagation Delay
EQ = 11,
+4.0 dB @ 2.5 GHz , Figure 4
(Note 9)
Differential
Propagation Delay
EQ = FF,
Equalizer Bypass, Figure 4
(Notes 9, 8)
Lane to Lane Skew in a T_A = 25C,V_DD = 2.5V
Single Part
(Notes 7, 8)
Part to Part
Propagation Delay
Skew
T_A = 25C,V_DD = 2.5V
Min
Typ
Max
Units
25
mV
6.5
9.5
nS
5.5
8
nS
150
200
250
ps
120
170
220
ps
27
ps
35
ps
11
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