DS50PCI401 Datasheet, PDF (4/32 Pages) National Semiconductor (TI) – 2.5 Gbps / 5.0 Gbps 4 Lane PCI Express Transceiver with Equalization and De-Emphasis

Pin Descriptions
Pin Name
Pin Number I/O, Type Pin Description
Differential High Speed I/O's
IA_0+, IA_0- ,
IA_1+, IA_1-,
IA_2+, IA_2-,
IA_3+, IA_3-
10, 11
12, 13
15, 16
17, 18
I, CML
Inverting and non-inverting CML differential inputs to the
equalizer. A gated on-chip 50Ω termination resistor connects
INA_0+ to VDD and INA_0- to VDD when enabled.
OA_0+, OA_0-,
OA_1+, OA_1-,
OA_2+, OA_2-,
OA_3+, OA_3-
35, 34
33, 32
31, 30
29, 28
O,LPDS
Inverting and non-inverting low power differential signal
(LPDS) 50Ω driver outputs with de-emphasis. Compatible
with AC coupled CML inputs.
IB_0+, IB_0- ,
IB_1+, IB_1-,
IB_2+, IB_2-,
IB_3+, IB_3-
45, 44
43, 42
40, 39
38, 37
I, CML
Inverting and non-inverting CML differential inputs to the
equalizer. A gated on-chip 50Ω termination resistor connects
INB_0+ to VDD and INB_0- to VDD when enabled.
OB_0+, OB_0-,
1, 2
OB_1+, OB_1-,
3, 4
OB_2+, OB_2-,
5, 6
OB_3+, OB_3-
7, 8
O,LPDS
Inverting and non-inverting low power differential signal
(LPDS) 50Ω driver outputs with de-emphasis. Compatible
with AC coupled CML inputs.
Control Pins — Shared (LVCMOS)
ENSMB
48
I, LVCMOS w/ System Management Bus (SMBus) enable pin.
internal
When pulled high provide access internal digital registers that
pulldown
are a means of auxiliary control for such functions as
equalization, de-emphasis, VOD, rate, and idle detection
threshold.
When pulled low, access to the SMBus registers are disabled
and SMBus function pins are used to control the Equalizer
and De-Emphasis.
Please refer to “SMBus configuration Registers” section and
Electrical Characteristics - Serial Management Bus Interface
for detail information.
ENSMB = 1 (SMBUS MODE)
SCL
50
I, LVCMOS ENSMB = 1
SMBUS clock input pin is enabled.
SDA,
49
I, LVCMOS, ENSMB = 1
O, OPEN
The SMBus bi-directional SDA pin is enabled. Data input or
Drain
open drain (pulldown only) output.
AD0-AD3
54, 53, 47, 46 I, LVCMOS w/ ENSMB = 1
internal
SMBus Slave Address Inputs. In SMBus mode, these pins are
pulldown
the user set SMBus slave address inputs.
ENSMB = 0 (NORMAL PIN MODE)
EQA0, EQA1
EQB0, EQB1
20, 19
46, 47
I,FLOAT,
LVCMOS
EQA/B ,0/1 controls the level of equalization of the A/B sides
as shown in Table 1. The EQA/B pins are active only when
ENSMB is de-asserted (Low). Each of the 4 A/B channels
have the same level unless controlled by the SMBus control
registers. When ENSMB goes high the SMBus registers
provide independent control of each lane, and the EQB0/B1
pins are converted to SMBUS AD2/AD3 inputs.
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