DS50PCI401 Datasheet, PDF (5/32 Pages) National Semiconductor (TI) – 2.5 Gbps / 5.0 Gbps 4 Lane PCI Express Transceiver with Equalization and De-Emphasis

Pin Name
Pin Number I/O, Type
Pin Description
DEMA0, DEMA1
DEMB0, DEMB1
49, 50
53, 54
I,FLOAT,
LVCMOS
DEMA/B ,0/1 controls the level of de-emphasis of the A/B
sides as shown in Table 2. The DEMA/B pins are only active
when ENSMB is de-asserted (Low). Each of the 4 A/B
channels have the same level unless controlled by the SMBus
control registers. When ENSMB goes High the SMBus
registers provide independent control of each lane and the
DEM pins are converted to SMBUS AD0/AD1 and SCL/SDA
inputs.
RATE
21
I,FLOAT,
RATE control pin controls the pulse width of de-emphasis of
LVCMOS
the output. A Low forces Gen1 (2.5Gbps), High forces Gen 2
(5Gbps), Open/Floating the rate is internally detected after
each exit from idle and the pulse width is set appropriately.
When ENSMBUS= 1 this pin is disabled and the RATE
function is controlled internally by the SMBUS registers. Refer
to Table 2.
Control Pins — Both Modes (LVCMOS)
RXDETA,RXDETB 22,23
I, LVCMOS w/ The RXDET pins in combination with the ENRXDET pin
internal
controls the receiver detect function. Depending on the input
pulldown
level, a 50Ω or >50KΩ termination to the power rail is enabled.
Refer to Table 5.
PRSNT
52
I, LVCMOS Cable Present Detect input. High when a cable is not present
per PCIe Cabling Spec. 1.0. Puts part into low power mode.
When low (normal operation) part is enabled.
ENRXDET
26
I, LVCMOS w/ Enables pin control of receiver detect function. Pin must be
internal
pulled high externally for RXDETA/B to function. Controls
pulldown
both A and B sides. Refer to Table 5.
TXIDLEA,TXIDLEB 24,25
I, FLOAT,
LVCMOS
Controls the electrical idle function on corresponding outputs
when enabled. H= electrical Idle, Float=autodetect (Idle on
input passed to output), L=Idle squelch disabled as shown in
Table 3.
Analog
SD_TH
27
I, ANALOG Threshold select pin for electrical idle detect threshold. Float
pin for default 130mV DIFF p-p, otherwise connect resistor
from SD_TH to GND to set threshold voltage as shown in
Table 4.
Power
VDD
9, 14,36, 41, Power
51
Power supply pins CML/analog.
GND
DAP
Power
Ground pad (DAP - die attach pad).
Notes:
FLOAT = 3rd input state, don't drive pin. Pin is internally biased to mid level with 50 kΩ pull-up/pull-down. If high Z
output not available, drive input to VDD/2 to assert mid level state.
Internal pulldown = Internal 30 kΩ pull-down resistor to GND is present on the input.
LVCMOS inputs without the “Float” conditions must be driven to a logic Low or High at all times or operation is not
guaranteed.
Input edge rate for LVCMOS/FLOAT inputs must be faster than 50 ns from 10–90%.
Functional Description
The DS50PCI401 is a low power media compensation 4 lane
transceiver optimized for PCI Express Gen 1 and Gen 2 me-
dia including lossy FR-4 printed circuit board backplanes and
balanced cables. The DS50PCI401 operates in two modes:
Pin Control Mode (ENSMB = 0) and SMBus Mode (ENSMB
= 1).
Pin Control Mode:
When in pin mode (ENSMB = 0) , the transceiver is config-
urable with external pins. Equalization and de-emphasis can
be selected via pin for each side independently. When de-
emphasis is asserted VOD is automatically increased per the
De-Emphasis table below for improved performance over
lossy media. The receiver detect pins RXDETA/B provide
manual control for input termination (50Ω or >50KΩ). Rate
optimization is also pin controllable, with pin selections for
2.5Gbps, 5Gbps, and auto detect. The receiver electrical idle
detect threshold is also programmable via an optional exter-
nal resistor on the SD_TH pin.
5
www.national.com