DS90UR241Q Datasheet, PDF (7/26 Pages) National Semiconductor (TI) – 5-43 MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Chipset

Note 11: UI – Unit Interval, equivalent to one ideal serialized data bit width. The UI scales with frequency.
Note 12: Figures 1, 2 Figures 8, 12, 14show a falling edge data strobe (TCLK IN/RCLK OUT).
Note 13: Figures 5, 15, 16 show a rising edge data strobe (TCLK IN/RCLK OUT).
Note 14: TxOUT_E_O is affected by pre-emphasis value.
AC Timing Diagrams and Test Circuits
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FIGURE 1. Serializer Input Checkerboard Pattern
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FIGURE 2. Deserializer Output Checkerboard Pattern
FIGURE 3. Serializer LVDS Output Load and Transition Times
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