DS90UR241Q Datasheet, PDF (16/26 Pages) National Semiconductor (TI) – 5-43 MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Chipset

Pin # Pin Name
I/O/PWR
Description
49 PTOSEL
LVCMOS_I
Progressive Turn On Operation Selection
PTO = H; R_OUT[23:0] are grouped into three groups of eight, with each group switching about
±1 UI to ±2 UI apart relative to RCLK. (Figure 15)
PTO = L; PTO Spread Mode, R_OUT[23:0] outputs are spread ±1 UI to ±2 UI and RCLK spread
±1 UI. (Figure 16) See Applications Informations section for more details.
63 RAOFF
LVCMOS_I
Randomizer Control Input Pin (See Table 2 for more details.)
RAOFF = H, Backwards compatible mode for use with DS90C241 Serializer.
RAOFF = L; Additional randomization ON (Default), Selects 2E7 LSFR setting.
64 SLEW
LVCMOS_I
LVCMOS Output Slew Rate Control
SLEW = L; Low drive output at 2 mA (default)
SLEW = H; High drive output at 4 mA
23 LOCK
50 RES0
LVCMOS_O
LVCMOS_I
LOCK indicates the status of the receiver PLL
LOCK = H; receiver PLL is locked
LOCK = L; receiver PLL is unlocked, R_OUT[23-0] and RCLK are at TRI-STATE.
Reserved. This pin MUST be tied LOW.
1-6, RES0
NC
17, 18,
33, 34
No Connection. Pins are not physically connected to the die. Recommendation is to leave pin
open or tie it to LOW.
BIST MODE PINS(See Applications Informations section for more details.)
61 BISTEN
LVCMOS_I
Control Pin for BIST Mode Enable
BISTEN = L; Default at Low, Normal Mode.
BISTEN = H; BIST mode active. When BISTEN = H and DS90UR241 DIN[23:0] = Low or
Floating; device will go to BIST mode accordingly. Check PASS output pin for test status.
62 BISTM
LVCMOS_I
BIST Mode selection. Control pin for which Deserializer is set for BIST reporting mode.
BISTM = L; Default at Low, Status of all R_OUT with respective bit error on cycle-by-cycle basis
BISTM = H; Total accumulated bit error count provided on ROUT[7:0] (binary counter up to 255)
45 PASS
LVCMOS_O
Pass flag output for @Speed BIST Test operation.
PASS = L; BIST failure
PASS = H; LOCK = H before BIST can be enabled, then 1x10^-9 error rate achieved across link.
LVDS SERIAL INTERFACE PINS
53
R_IN+
LVDS_I
54
R_IN−
LVDS_I
POWER / GROUND PINS
Receiver LVDS True (+) Input — This input is intended to be terminated with a 100Ω load to
the R_IN+ pin. The interconnect should be AC Coupled to this pin with a 100 nF capacitor.
Receiver LVDS Inverted (−) Input — This input is intended to be terminated with a 100Ω load
to the R_IN- pin. The interconnect should be AC Coupled to this pin with a 100 nF capacitor.
51 VDD
VDD
Analog LVDS Voltage Supply, POWER
52 VSS
GND
Analog LVDS GROUND
59 VDD
VDD
Analog Voltage Supply, PLL POWER
58 VSS
GND
Analog Ground, PLL GROUND
57 VDD
VDD
Analog Voltage supply, PLL VCO POWER
56 VSS
GND
Analog Ground, PLL VCO GROUND
32 VDD
VDD
Digital Voltage Supply, LOGIC POWER
31 VSS
GND
Digital Ground, Logic GROUND
46 VDD
VDD
Digital Voltage Supply, LOGIC POWER
47 VSS
GND
Digital Ground, LOGIC GROUND
40 VDD
VDD
Digital Voltage Supply, LVCMOS Output POWER
39 VSS
GND
Digital Ground, LVCMOS Output GROUND
26 VDD
VDD
Digital Voltage Supply, LVCMOS Output POWER
25 VSS
GND
Digital Ground, LVCMOS Output GROUND
11 VDD
VDD
Digital Voltage Supply, LVCMOS Output POWER
12 VSS
GND
Digital Ground, LVCMOS Output GROUND
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