DS90UR241Q Datasheet, PDF (21/26 Pages) National Semiconductor (TI) – 5-43 MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Chipset

FIGURE 19. DS90UR124 Typical Application Connection
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PCB LAYOUT AND POWER SYSTEM CONSIDERATIONS
Circuit board layout and stack-up for the LVDS SERDES de-
vices should be designed to provide low-noise power feed to
the device. Good layout practice will also separate high fre-
quency or high-level inputs and outputs to minimize unwanted
stray noise pickup, feedback and interference. Power system
performance may be greatly improved by using thin di-
electrics (2 to 4 mils) for power / ground sandwiches. This
arrangement provides plane capacitance for the PCB power
system with low-inductance parasitics, which has proven es-
pecially effective at high frequencies, and makes the value
and placement of external bypass capacitors less critical. Ex-
ternal bypass capacitors should include both RF ceramic and
tantalum electrolytic types. RF capacitors may use values in
the range of 0.01 uF to 0.1 uF. Tantalum capacitors may be
in the 2.2 uF to 10 uF range. Voltage rating of the tantalum
capacitors should be at least 5X the power supply voltage
being used.
Surface mount capacitors are recommended due to their
smaller parasitics. When using multiple capacitors per supply
pin, locate the smaller value closer to the pin. A large bulk
capacitor is recommend at the point of power entry. This is
typically in the 50uF to 100uF range and will smooth low fre-
quency switching noise. It is recommended to connect power
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