DS90UR241Q Datasheet, PDF (12/26 Pages) National Semiconductor (TI) – 5-43 MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Chipset

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FIGURE 15. Deserializer Setup and Hold Times and PTO, PTOSEL = H
Group 1 will be latched internally by sequence of (early 2UI, late 1UI, early 1UI, late 2UI)
Group 2 will be latched internally by sequence of (late 1UI, early 1UI, late 2UI, early 2UI)
Group 3 will be latched internally by sequence of (early 1UI, late 2UI, early 2UI, late 1UI)
FIGURE 16. Deserializer Setup and Hold Times and PTO Spread, PTOSEL = L
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