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DS90UR241Q Datasheet, PDF (4/26 Pages) National Semiconductor (TI) – 5-43 MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Chipset
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Symbol
Parameter
Conditions
Pin/Freq.
Min Typ Max Units
LVDS DC SPECIFICATIONS
VTH
Differential Threshold High VCM = +1.8V
Voltage
Rx: RIN+, RIN−
+50 mV
VTL
Differential Threshold Low
Voltage
−50
mV
IIN
Input Current
VIN = +2.4V, VDD = 3.6V
VIN = 0V, VDD = 3.6V
VOD
Output Differential Voltage
RL = 100Ω, w/o pre- VODSEL = L Tx: DOUT+, DOUT−
(DOUT+)–(DOUT−)
emphasis (Figure 10) VODSEL = H
±100 ±250 µA
±100 ±250 µA
380 500 630
mV
500 900 1100
ΔVOD
Output Differential Voltage
Unbalance
RL = 100Ω,
w/o pre-emphasis
VODSEL = L
VODSEL = H
1 50 mV
VOS
Offset Voltage
RL = 100Ω,
w/o pre-emphasis
VODSEL = L
VODSEL = H
1.00 1.25 1.50 V
ΔVOS Offset Voltage Unbalance
RL = 100Ω,
w/o pre-emphasis
VODSEL = L
VODSEL = H
3 50 mV
IOS
Output Short Circuit Current DOUT = 0V, DIN = H, VODSEL = L
TPWDNB = 2.4V
VODSEL = H
−2.0 −5.0 −8.0
mA
−4.5 −7.9 −14.0
IOZ
TRI-STATE Output Current TPWDNB = 0V,
DOUT = 0V OR VDD
TPWDNB = 2.4V, DEN = 0V
DOUT = 0V OR VDD
TPWDNB = 2.4V, DEN = 2.4V,
DOUT = 0V OR VDD
NO LOCK (NO TCLK)
−15 ±1 +15 µA
−15 ±1 +15 µA
−15 ±1 +15 µA
SER/DES SUPPLY CURRENT (DVDD*, PVDD* AND AVDD* PINS) *DIGITAL, PLL, AND ANALOG VDDS
IDDT
Serializer
Total Supply Current
(includes load current)
RL = 100Ω, PRE = OFF,
RAOFF = H, VODSEL = L
RL = 100Ω, PRE = 12 kΩ,
RAOFF = H, VODSEL = L
f = 43 MHz,
CHECKER BOARD
Pattern (Figure 1)
60 85 mA
65 90 mA
RL = 100Ω, PRE = OFF,
RAOFF = H, VODSEL = H
f = 43 MHz,
RANDOM pattern
66 90 mA
IDDTZ
Serializer
TPWDNB = 0V
Supply Current Power-down (All other LVCMOS Inputs = 0V)
45 µA
IDDR
Deserializer
Total Supply Current
(includes load current)
CL = 4 pF,
SLEW = H
f = 43 MHz,
CHECKER BOARD
Pattern LVCMOS
Output (Figure 2)
85 105 mA
CL = 4 pF,
SLEW = H
f = 43 MHz,
RANDOM pattern
LVCMOS Output
80 100 mA
IDDRZ
Deserializer
Supply Current Power-down
RPWDNB = 0V
(All other LVCMOS Inputs = 0V,
RIN+/RIN- = 0V)
50 µA
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