DS90UR241Q Datasheet, PDF (6/26 Pages) National Semiconductor (TI) – 5-43 MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Chipset

Symbol
Parameter
Conditions
Pin/Freq.
t_ROS
R_OUT (0:7) Setup Data to
PTOSEL = L,
R_OUT[0:7]
RCLK (Group 1)
SLEW = H,
t_ROH
R_OUT (0:7) Hold Data to RCLK ^{(Figure 16)}
(Group 1)
t_ROS
R_OUT (8:15) Setup Data to PTOSEL = L,
R_OUT [8:15],
RCLK (Group 2)
SLEW = H,
LOCK
t_ROH
R_OUT (8:15) Hold Data to
(Figure 16)
RCLK (Group 2)
t_ROS
R_OUT (16:23) Setup Data to
RCLK (Group 3)
R_OUT [16:23]
t_ROH
R_OUT (16:23) Setup Data to
RCLK (Group 3)
t_ROS
R_OUT (0:7) Setup Data to
PTOSEL = H,
R_OUT[0:7]
RCLK (Group 1)
SLEW = H,
t_ROH
R_OUT (0:7) Hold Data to RCLK ^{(Figure 15)}
(Group 1)
t_ROS
R_OUT (8:15) Setup Data to
RCLK (Group 2)
R_OUT [8:15],
LOCK
t_ROH
R_OUT (8:15) Hold Data to
RCLK (Group 2)
t_ROS
R_OUT (16:23) Setup Data to
RCLK (Group 3)
R_OUT [16:23]
t_ROH
R_OUT (16:23) Setup Data to
RCLK (Group 3)
t_HZR
HIGH to TRI-STATE Delay PTOSEL = H, R_OUT [0:23],
t_LZR
LOW to TRI-STATE Delay ^{(Figure 14)}
RCLK, LOCK
t_ZHR
TRI-STATE to HIGH Delay
t_ZLR
TRI-STATE to LOW Delay
t_DD
Deserializer Delay
PTOSEL = H,
(Figure 12)
RCLK
t_DSR
Deserializer PLL Lock Time (Note 7, Note 9) 5 MHz
from Powerdown
43 MHz
RxIN_TOL-L Receiver INput TOLerance
Left
(Note 8, Note 9), 5 MHz–43 MHz
(Note 11)
(Figure 17)
RxIN_TOL-R Receiver INput TOLerance
Right
(Note 8),(Note 9, 5 MHz–43 MHz
Note 11)
(Figure 17)
Min
(0.35)*
t_RCP
(0.35)*
t_RCP
(0.35)*
t_RCP
(0.35)*
t_RCP
(0.35)*
t_RCP
(0.35)*
t_RCP
(0.35)*
t_RCP
(0.35)*
t_RCP
(0.35)*
t_RCP
(0.35)*
t_RCP
(0.35)*
t_RCP
(0.35)*
t_RCP
Typ
(0.5*t_RCP)–3 UI
Max Units
ns
(0.5*t_RCP)–3 UI
ns
(0.5*t_RCP)–3 UI
ns
(0.5*t_RCP)–3 UI
ns
(0.5*t_RCP)–3 UI
ns
(0.5*t_RCP)–3 UI
ns
(0.5*t_RCP)–2 UI
ns
(0.5*t_RCP)+2 UI
ns
(0.5*t_RCP)−1 UI
ns
(0.5*t_RCP)+1 UI
ns
(0.5*t_RCP)+1 UI
ns
(0.5*t_RCP)–1 UI
ns
3
10
ns
3
10
ns
3
10
ns
3
10
ns
[5+(5/56)]T ns
[5+(5/56)]T+3.7
+8
128k*T ms
128k*T ms
0.25
UI
0.25
UI
Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the
device should not be operated beyond such conditions.
Note 2: 4L =4 layer PCB per JEDEC specification, 2L = 2 layer PCB per JEDEC specification.
Note 3: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
Note 4: Typical values represent most likely parametric norms at V_DD = 3.3V, Ta = +25 degC, and at the Recommended Operation Conditions at the time of
product characterization and are not guaranteed.
Note 5: Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground except VOD, ΔVOD,
VTH and VTL which are differential voltages.
Note 6: When the Serializer output is at TRI-STATE the Deserializer will lose PLL lock. Resynchronization MUST occur before data transfer.
Note 7: t_DSR is the time required by the Deserializer to obtain lock when exiting powerdown mode.
Note 8: RxIN_TOL is a measure of how much phase noise (jitter) the Deserializer can tolerate in the incoming data stream before bit errors occur. It is a
measurement in reference with the ideal bit position, please see National’s AN-1217 for detail.
Note 9: Specification is guaranteed by characterization and is not tested in production.
Note 10: t_JIT (@BER of 10e-9) specifies the allowable jitter on TCLK. t_JIT not included in TxOUT_E_O parameter.
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