DS90UR241Q Datasheet, PDF (20/26 Pages) National Semiconductor (TI) – 5-43 MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Chipset

FIGURE 18. DS90UR241 Typical Application Connection
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POWER CONSIDERATIONS
An all LVCMOS design of the Serializer and Deserializer
makes them inherently low power devices. Additionally, the
constant current source nature of the LVDS outputs minimize
the slope of the speed vs. I_DD curve of LVCMOS designs.
NOISE MARGIN
The Deserializer noise margin is the amount of input jitter
(phase noise) that the Deserializer can tolerate and still reli-
ably recover data. Various environmental and systematic fac-
tors include:
Serializer: V_DD noise, TCLK jitter (noise bandwidth and
out-of-band noise)
Media: ISI, V_CM noise
Deserializer: V_DD noise
For a graphical representation of noise margin, please see .
TRANSMISSION MEDIA
The Serializer and Deserializer are to be used in point-to-point
configuration, through a PCB trace, or through twisted pair
cable. In a point-to-point configuration, the transmission me-
dia needs be terminated at both ends of the transmitter and
receiver pair. Interconnect for LVDS typically has a differential
impedance of 100 Ohms. Use cables and connectors that
have matched differential impedance to minimize impedance
discontinuities. In most applications that involve cables, the
transmission distance will be determined on data rates in-
volved, acceptable bit error rate and transmission medium.
LIVE LINK INSERTION
The Serializer and Deserializer devices support live plug-
gable applications. The automatic receiver lock to random
data “plug & go” hot insertion capability allows the
DS90UR124 to attain lock to the active data stream during a
live insertion event.
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