DS90UR241Q Datasheet, PDF (15/26 Pages) National Semiconductor (TI) – 5-43 MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Chipset

DS90UR124 Pin Diagram
Deserializer - DS90UR124
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20194520
DS90UR124 Deserializer Pin Descriptions
Pin # Pin Name I/O/PWR
Description
LVCMOS PARALLEL INTERFACE PINS
35-38, R_OUT[7:0]
41-44
LVCMOS_O Receiver Parallel Interface Data Outputs – Group 1
19-22, R_OUT[15:8]
27-30
LVCMOS_O Receiver Parallel Interface Data Outputs – Group 2
7-10, R_OUT[23:16] LVCMOS_O Receiver Parallel Interface Data Outputs – Group 3
13-16
24 RCLK
LVCMOS_O Parallel Interface Clock Output Pin. Strobe edge set by RRFB configuration pin.
CONTROL AND CONFIGURATION PINS
55 RRFB
60 REN
LVCMOS_I
LVCMOS_I
Receiver Clock Edge Select Pin
RRFB = H; R_OUT LVCMOS Outputs strobed on the Rising Clock Edge.
RRFB = L; R_OUT LVCMOS Outputs strobed on the Falling Clock Edge.
Receiver Data Enable
REN = H; R_OUT[23-0] and RCLK are Enabled (ON).
REN = L; R_OUT[23-0] and RCLK are Disabled (OFF), Receiver R_OUT[23-0] and RCLK Outputs
are in TRI-STATE, PLL still operational and locked to TCLK.
48 RPWDNB LVCMOS_I Receiver Power Down Bar
RPWDNB = H; Receiver is Enabled and ON
RPWDNB = L; Receiver is in power down mode (Sleep), R_OUT[23-0], RCLK, and LOCK are in
TRI-STATE stand-by mode, PLL is shutdown to minimize power consumption.
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