DS90UR241Q Datasheet, PDF (13/26 Pages) National Semiconductor (TI) – 5-43 MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Chipset

RxIN_TOL_L is the ideal noise margin on the left of the figure, with respect to ideal.
RxIN_TOL_R is the ideal noise margin on the right of the figure, with respect to ideal.
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FIGURE 17. Receiver Input Tolerance (RxIN_TOL) and Sampling Window
DS90UR241 Pin Diagram
Serializer - DS90UR241
TOP VIEW
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DS90UR241 Serializer Pin Descriptions
Pin # Pin Name I/O/PWR
Description
LVCMOS PARALLEL INTERFACE PINS
4-1, D_IN[23:0]
48-44,
41-32,
29-25
LVCMOS_I Transmitter Parallel Interface Data Input Pins. Tie LOW if unused, do not float.
10 TCLK
LVCMOS_I Transmitter Parallel Interface Clock Input Pin. Strobe edge set by TRFB configuration pin.
13
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