CS5535 Datasheet, PDF (60/555 Pages) National Semiconductor (TI) – Geode™ CS5535 I/O Companion Multi-Function South Bridge

Global Concepts and Features (Continued)
3.7 MEMORY AND I/O MAP OVERVIEW
3.7.1 Introduction
There are several places in the CS5535 where addresses
are decoded and routed:
• Physical PCI Bus: The GLPCI_SB decodes PCI bus
transactions and claims them with a “DEVSEL#” as
appropriate. After claiming a transaction, the GLPCI_SB
converts it to a GLIU request packet. It then passes the
request to the GLIU. It has no routing control or respon-
sibility beyond this point.
• GLIU: The GLIU compares the request addresses
against the descriptor settings. It passes the request to
the port associated with the compare hit. Each port is
connected to a specific GeodeLink Device (see Section
3.1.5 "Topology" on page 52 for port assignment). There
are also specific legacy addresses that receive “special”
routing beyond the standard descriptor routing mecha-
nisms.
• Typical GeodeLink Device: For most GeodeLink
Devices, further decoding is minimal. If a device
contains only MSRs and a single native block (register
group) in I/O or memory space, specific bits within the
request packet can be used to easily select between the
two. If a device contains more than one register group, a
Local Base Address Register (LBAR) for each group is
used. Like a PCI Base Address Register (BAR), an
LBAR compare and hit operation is used to select the
desired group.
• Diverse Device: The Diverse Device has the same
decoding responsibilities as a typical GeodeLink Device.
Beyond this programmable LBAR decoding, it has
substantial fixed decoding associated with legacy
addresses.
3.7.2 PCI Bus Decoding
From reset, the GLPCI_SB does not actively decode any-
thing. However, it will subtractively decode everything.
From reset, everything not positively claimed on the PCI
bus is converted to a GLIU request and passed to the
GLIU.
Using appropriate setup registers, the GLPCI_SB can be
programmed to actively decode selected I/O and memory
regions. Other than actively claiming, the “convert” and
“pass” operation is the same.
There are also control bits in the GLPCI_MSR_CTL (MSR
51700010h) register to regulate behavior associated with
legacy addresses:
• Bits [12:11]: Legacy I/O Space Active Decode. These
bits control the degree to which the GLPCI_SB will
actively claim I/O region 0000h through 03FFh:
— 00: Subtractive – Claim on fourth clock. (Default.)
— 01: Slow – Claim on third clock.
— 10: Medium – Claim on second clock.
• Bit 13: Reject Primary IDE. If this bit is set, the
GLPCI_SB will not actively decode the primary IDE
addresses of: 01F0h/01F7h and 03F6h.
• Bit 14: Reject Secondary IDE. If this bit is set, the
GLPCI_SB will not actively decode the secondary IDE
addresses of: 0170h/0177h and 0376h.
• Bit 15: Reject DMA High Page Active. If this bit is set, the
GLPCI_SB will actively decode the following I/O range
associated with the DMA High Page registers:
0480h/048Fh.
For further details on the GLPCI_MSR_CTL register see
Section 5.2.2.1 "Global Control (GLPCI_CTRL)" on page
219.
Lastly, there in an “MSR Access Mailbox” located in PCI
Configuration register space. It consists of the following 32-
bit registers:
• MSR Address (PCI Index F4h). Full MSR routing path in
the upper portion plus 14 device address bits in the
lower portion.
• MSR Data Low (PCI Index F8h). Bits [31:0]: When read,
an MSR cycle is generated. The 64-bit read returns the
low 32 bits and saves the upper 32 bits for a read to
“Data High”. A write holds the value written as the
current “Data Low”.
• MSR Data High (PCI Index FCh). Bits [63:32]: Reads
return upper 32 bits of the last MSR value read. Writes
generate an MSR write cycle using the current value
and the “Data Low” value.
For further details on the MSR Access Mailbox see Section
5.2.3 "PCI Configuration Registers" on page 225.
3.7.3 GLIU Decoding
From reset, the GLIU passes all request packets to the
Diverse Device, except for the legacy primary IDE
addresses (01F0h/01F7h and 03F6h), these are passed to
the IDE device in the ATAC. There is a GLIU IOD_SC
descriptor to control this primary IDE behavior and it
defaults configured (see Section 5.1.4.2 "IOD Swiss
Cheese Descriptors (GLIU_IOD_SC[x])" on page 211). If
this descriptor is disabled, all requests pass to the Diverse
Device.
Using appropriate MSR setup registers (descriptors), the
GLIU can be programmed to route selected I/O and mem-
ory regions to specific GeodeLink Devices. Any memory or
I/O address that does not hit one of these regions, subtrac-
tively routes to the Diverse Device. Unlike PCI, there is no
performance loss associated with being the subtractive
port.
Operationally, there are five bus masters within the
CS5535: ATAC, ACC, DD, USBC1, and USBC2. These
masters only generate requests to access main memory off
the GX2. Therefore, all their GLIU requests need to be
routed to the GLPCI_SB for presentation to the PCI bus. A
set of GLIU P2D_BM descriptors could be used for this
purpose. However, the CS5535 GLIU is uniquely modified
to route all requests for the listed masters to the GLPCI_SB
unconditionally. Therefore, GLIU P2D_BM settings do not
www.national.com
60
Revision 0.8