CS5535 Datasheet, PDF (41/555 Pages) National Semiconductor (TI) – Geode™ CS5535 I/O Companion Multi-Function South Bridge

Signal Definitions (Continued)
2.2.7 Audio Codec 97 InterfaceNote 1
Signal Name
Ball No.
Type
AC_CLK
M1
I
AC_S_OUT
L2
O
BOS1
I
AC_S_IN
L1
I
AC_S_SYNC
L3
O
BOS0
I
AC_BEEP
AC_S_IN2
K3
O
J3
I
Note 1. Use RESET_OUT# for AC97 reset.
Description
Audio Bit Clock. The serial bit clock from the codec. The frequency of
the bit clock is 12.288 MHz and is derived from the 24.576 MHz crystal
input to the external audio codec. Not required if audio not used; tie low.
Audio Controller Serial Data Out. This output transmits audio data to
the codec. This data stream contains both control data and the DAC
audio data. The data is sent on the rising edge of the AC_CLK. Connect
to the audio codec’s serial data input pin.
Boot Options Select Bit 1. During system reset, this ball is the MSB of
the two-bit boot option (balls L2 and L3), used to determine the location
of the system boot device. It should be pulled low if required by Table 2-5
"Boot Options Selection" on page 29, otherwise, an internal pull up,
asserted during reset, will pull it high. During reset, the ball output driv-
ers are held in TRI-STATE, and the ball is sampled on the rising edge of
RESET_OUT# (i.e., when external reset is de-asserted). After reset, this
signal defaults low (off).
Audio Controller Serial Data Input. This input receives serial data from
the audio codec. This data stream contains both control data and ADC
audio data. This input data is sampled on the falling edge of
AC_CLK.Connect to the audio codec’s serial data output pin.
Audio Controller Sync. This is a 48 kHz sync pulse that signifies the
beginning of a serial transfer on AC_S_OUT, AC_S_IN, and AC_S_IN2.
AC_S_SYNC is synchronous to the rising edge of AC_CLK. Connect to
the audio codec’s SYNC pin.
Boot Options Select Bit 0. During system reset, this ball is the LSB of
the two-bit boot option (balls L2 and L3), used to determine the location
of the system boot device. It should be pulled low if required by Table 2-5
"Boot Options Selection" on page 29, otherwise, an internal pull up,
asserted during reset, will pull it high. During reset, the ball drivers are
held in TRI-STATE, and the ball is sampled on the rising edge of
RESET_OUT# (i.e., when external reset is de-asserted). After reset, this
signal defaults low (off).
Legacy PC/AT Speaker Beep. Connect to codec’s PC_BEEP.
This function is only available when GPIO1 is programmed to
AUX_OUT_1. See Table 2-8 "GPIO Options" on page 42.
Audio Controller Serial Data Input 2. This input receives serial data
from a second codec. This data stream contains both control data and
ADC audio data. This input data is sampled on the falling edge of
AC_CLK. If the codec’s Ready bit is set in this stream (slot 0, bit 15),
then it is functionally ORed with AC_S_IN.
Connect to a second codec’s serial data output.
This function is only available when GPIO12 is programmed to AUX_IN.
See Table 2-8 "GPIO Options" on page 42.
Revision 0.8
41
www.national.com