CS5535 Datasheet, PDF (276/555 Pages) National Semiconductor (TI) – Geode™ CS5535 I/O Companion Multi-Function South Bridge

USB Register Descriptions (Continued)
5.5.3.15 Maximum Latency (USBC_PCI_MAX_LTNCY)
Index
3Fh
Type
R/W
Reset Value
50h
USBC_PCI_MAX_LTNCY Register Map
7
6
5
4
3
2
1
0
MAX_LTNCY
Bit Name
7:0 MAX_LTNCY
USBC_PCI_MAX_LTNCY Bit Descriptions
Description
Maximum Latency. This register specifies the desired settings for how often the USB
needs access to the PCI bus assuming a clock rate of 33 MHz. The value specifies a
period of time in units of 1/4 microsecond.
5.5.3.16 ASIC Test Mode Enable (USBC_PCI_ASIC_TEST)
Index
40h
Type
R/W
Reset Value
000F0000h
USBC_PCI_ASIC_TEST Register Map
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
Bit Name
31:0 RSVD
USBC_PCI_ASIC_TEST Bit Descriptions
Description
Reserved. These bits are reserved for internal testing only. These bits should not be
written to.
5.5.3.17 ASIC Operational Mode Enable (USBC_PCI_ASIC_MODE)
Index
44h
Type
R/W
Reset Value
0000h
USBC_PCI_ASIC_MODE Register Map
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RSVD
RSVD
Bit Reset
15:9 RSVD
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USBC_PCI_ASIC_MODE Bit Descriptions
Description
Reserved. Write 0s; reads undefined.
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Revision 0.8