CS5535 Datasheet, PDF (447/555 Pages) National Semiconductor (TI) – Geode™ CS5535 I/O Companion Multi-Function South Bridge

GPIO Subsystem Register Descriptions (Continued)
5.16.2.15 GPIO Input Positive Edge Enable (GPIO[x]_IN_POSEDGE_EN)
These registers control the enabling of the positive edge detector function for the low (GPIO[15:0]) and high (GPIO[31:16])
banks of GPIOs. The positive edge detector function is enabled if the feature bit is high. The positive edge detector function
is disabled if the feature bit is low. (These registers use atomic programming, see Section 5.16.1 on page 436 for details.)
GPIO Low Bank Input Positive Edge Enable
(GPIOL_IN_POSEDGE_EN)
GPIO I/O Offset 40h
Type
R/W
Reset Value
FFFF0000h
GPIO High Bank Input Positive Edge Enable
(GPIOH_IN_POSEDGE_EN)
GPIO I/O Offset C0h
Type
R/W
Reset Value
FFFF0000h
GPIOL_IN_POSEDGE_EN Register Map
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIOH_IN_POSEDGE_EN Register Map
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
5.16.2.16 GPIO Input Negative Edge Enable (GPIO[x]_IN_NEGEDGE_EN)
These registers control the enabling of the negative edge detector function in the inputs for the low (GPIO[15:0]) and high
(GPIO[31:16]) banks of GPIOs. The negative edge detector function is enabled if the feature bit is high. The negative edge
detector function is disabled if the feature bit is low. (These registers use atomic programming, see Section 5.16.1 on page
436 for details.)
GPIO Low Bank Input Negative Edge Enable
(GPIOL_IN_NEGEDGE_EN)
GPIO I/O Offset 44h
Type
R/W
Reset Value
FFFF0000h
GPIO High Bank Input Negative Edge Enable
(GPIOH_IN_NEGEDGE_EN)
GPIO I/O Offset C4h
Type
R/W
Reset Value
FFFF0000h
GPIOL_IN_NEGEDGE_EN Register Map
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIOH_IN_NEGEDGE_EN Register Map
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Revision 0.8
447
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