LP3971 Datasheet, PDF (4/42 Pages) National Semiconductor (TI) – POWER MANAGEMENT UNIT FOR ADVANCED APPLICATION PROCESSORS

Pin Descriptions
Pin #
Name
I/O Type
Description
1
PWR_ON
I
D CPU Wakeup input
2
nTEST_JIG
I
D CPU Wakeup input
3
SPARE
I
D CPU Wakeup input
4
EXT_WAKEUP
O
D CPU Wakeup output
5
FB1
I
A Buck1 Feedback
6
V_IN
I
P Battery Input (Internal circuitry and LDO1–3 power input)
7
V_OUT LDO1
O
P LDO1 output
8
V_OUT LDO2
O
P LDO2 output
9
nRSTI
I
D Reset Input
10
GND1
G
G Ground
11
V_REF
O
A Bypass Cap. for reference
12
V_OUT LDO3
O
P LDO3 output
13
V_OUT LDO4
O
P LDO4 output
14
V_IN LDO4
I
P Input power for LDO4
15
V_IN BUBATT
I
P Back Up Battery input
16
V_OUT LDO_RTC
O
P LDO_RTC output
17
nBATT_FLT
O
D Main Battery fault output
18
PGND2
G
G Buck2 NMOS Power Ground
19
SW2
O
P Buck2 Output
20
V_IN Buck2
I
P Buck2 battery input
21
SDA
I/O
D I²C Data
22
SCL
I
D I²C Clock
23
FB2
I
A Buck2 Feedback
24
nRSTO
O
D Reset output
25
V_OUT LDO5
O
P LDO5 output
26
V_IN LDO5
I
P Input power for LDO5
27
VDDA
I
P Analog Power
28
FB3
I
A Buck3 Feedback
29
GPIO1/nCHG_EN
I/O
D General Purpose I/O/Ext. backup battery charger enable
30
GPIO2
I/O
D General Purpose I/O
31
V_IN Buck3
I
P Buck3 battery input
32
SW3
O
P Buck3 Output
33
PGND3
G
G Buck3 NMOS Power Ground
34
BGND1,2,3
G
G Bucks 1, 2 and 3 analog Ground
35
SYNC
I
D Bucks external clock input
36
SYS_EN
I
D High voltage domain enable
37
PWR_EN
I
D Low Voltage domain enable
38
PGND1
G
G Buck1 NMOS Power Ground
39
SW1
O
P Buck1 Output
40
V_IN Buck1
I
P Buck1 battery input
A: Analog Pin
D: Digital Pin
G: Ground Pin
P: Power Pin
I: Input Pin
I/O: Input/Output Pin
O: Output Pin
Note: In this document active low logic items are prefixed with a lowercase “n”
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