LP3971 Datasheet, PDF (16/42 Pages) National Semiconductor (TI) – POWER MANAGEMENT UNIT FOR ADVANCED APPLICATION PROCESSORS

Buck Converter Operation (Continued)
SHUTDOWN MODE
During shutdown the PFET switch, reference, control and
bias circuitry of the converters are turned off. The NFET
switch will be on in shutdown to discharge the output. When
the converter is enabled, soft start is activated. It is recom-
mended to disable the converter during the system power up
and undervoltage conditions when the supply is less than
2.8V.
SOFT START
The buck converter has a soft-start circuit that limits in-rush
current during start-up. During start-up the switch current
limit is increased in steps. Soft start is activated only if EN
goes from logic low to logic high after V_IN reaches 2.8V. Soft
start is implemented by increasing switch current limit in
steps of 213 mA, 425 mA, 850 mA and 1700 mA (typ. Switch
current limit). The start-up time thereby depends on the
output capacitor and load current demanded at start-up.
Typical start-up times with 10 µF output capacitor and 1000
mA load current is 390 µs and with 1 mA load current its
295 µs.
LDO - LOW DROP OUT OPERATION
The LP3971 can operate at 100% duty cycle (no switching;
PMOS switch completely on) for low drop out support of the
output voltage. In this way the output voltage will be con-
trolled down to the lowest possible input voltage. When the
device operates near 100% duty cycle, output voltage ripple
is approximately 25 mV. The minimum input voltage needed
to support the output voltage is
I²C Compatible Interface
V_{IN, MIN} = I_LOAD * (R_{DSON, PFET} + R_INDUCTOR) + V_OUT
•I_LOAD
•R_{DSON, PFET}
Load Current
Drain to source resistance of PFET
switch in the triode region
•R_INDUCTOR
Inductor resistance
BUCK CONVERTER EFFICIENCY
V_IN (V)
3.6
3.6
3.6
3.6
V_OUT (V)
1.4
1.4
1.4
1.4
I_OUT (mA)
100
500
1000
1500
V_IN (V)
3.6
3.6
3.6
3.6
V_OUT (V)
3.3
3.3
3.3
3.3
I_OUT (mA)
100
500
1000
1500
V_IN (V)
3.6
3.6
3.6
3.6
V_OUT (V)
1.8
1.8
1.8
1.8
I_OUT (mA)
100
500
1000
1500
EFF(%)
85
89
84
78
EFF(%)
92
96
93
90
EFF(%)
85
91
87
82
I²C DATA VALIDITY
The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, state of the data line can
only be changed when CLK is LOW.
I²C START and STOP CONDITIONS
START and STOP bits classify the beginning and the end of
the I²C session. START condition is defined as SDA signal
transitioning from HIGH to LOW while SCL line is HIGH.
STOP condition is defined as the SDA transitioning from
LOW to HIGH while SCL is HIGH. The I²C master always
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generates START and STOP bits. The I²C bus is considered
to be busy after START condition and free after STOP con-
dition. During data transmission, I²C master can generate
repeated START conditions. First START and repeated
START conditions are equivalent, function-wise.
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