LP3971 Datasheet, PDF (38/42 Pages) National Semiconductor (TI) – POWER MANAGEMENT UNIT FOR ADVANCED APPLICATION PROCESSORS

Application Note (Continued)
Code Start Power on Timing
20180722
POWER-ON TIMING
Symbol
Description
Min
Typ
Max
Units
t1
Delay from VCC_RTC assertion to nRSTO de-assertion
50
mS
t3
Delay from nRST de-assertion to SYS_EN assertion
10
mS
t4
Delay from SYS_EN assertion to PWR_EN assertion
125
mS
t5
Delay from PWR_EN assertion to nRSTO de-assertion
125
mS
LP3971 & PXA27x RESET SEQUENCE
Hardware Reset Sequence
Hardware reset initiates when the nRSTI signal is asserted
(low). Upon assertion of nRST the processor enters hard-
ware reset state. The LP3971 holds the nRST low long
enough (50ms typ.) to allow the processor time to initiate the
reset state.
Reset Sequence
1. nRSTI is asserted
2. If V_BATT is above the set point the PMIC de-asserts
nBATT_FLT to indicate system power (V_IN) is available.
3. nRSTO is asserted and will de-asserts after a minimum
of 50 mS.
4. The Applications processor asserts SYS_EN, the
LP3971 enables the system high-voltage power sup-
plies. The Applications processor starts its countdown
timer set to 125 mS.
5. The LP3971 enables the high-voltage power supplies.
6. Countdown timer expires; the Applications processor
asserts PWR_EN to enable the low-voltage power sup-
plies. The processor starts the countdown timer set to
125 mS period.
7. The Applications processor asserts PWR_EN, the
LP3971 enables the low-voltage regulators.
8. Countdown timer expires; If enabled power domains are
OK (I²C read) the power up sequence continues by
enabling the processors 13 MHz oscillator and PLL’s.
9. The Applications processor begins the execution of
code.
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