LP3971 Datasheet, PDF (33/42 Pages) National Semiconductor (TI) – POWER MANAGEMENT UNIT FOR ADVANCED APPLICATION PROCESSORS

I ²C Register Definitions (Continued)
I²C DVM TIMING FOR VCC APPS (Buck 1)
20180718
LP3971 Controls
DIGITAL INTERFACE CONTROL SIGNALS
Signal
SYS_EN
PWR_EN
SCL
SDA
nRSTI
nRSTO
nBATT_FLT
PWR_ON
nTEST_JIG
SPARE
EXT_WAKEUP
GPIO1/nCHG_EN
GPIO2
*
Definition
High Voltage Power Enable
Low Voltage Power Enable
Serial Bus Clock Line
Serial Bus Data Line
Forces an Unconditional Hardware Reset
Forces an Unconditional Hardware Reset
Main Battery Removed or Discharged Indicator
Wakeup Input to CPU
Wakeup Input to CPU
Wakeup Input to CPU
Wake-Up Output for Application Processor
General Purpose I/O/External Back-Up Battery Charger
General Purpose I/O
Active State
High
High
Clock
Low
Low
Low
High
Low
High/Low*
High
-/Low
-
Signal Direction
Input
Input
Input
Bidirectional
Input
Output
Output
Input
Input
Input
Output
Bidirectional/Input
Bidirectional
POWER DOMAIN ENABLES
PMU Output
LDO_RTC
LDO1
LDO2
LDO3
LDO4
LDO5
BUCK1
BUCK2
BUCK3
HW Enable
-
SYS_EN
SYS_EN
SYS_EN
PWR_EN/SYS_EN
PWR_EN/SYS_EN
PWR_EN
SYS_EN/PWR_EN
SYS_EN
SW Enable
-
LDO1_EN
LDO2_EN
LDO3_EN
LDO4_EN
LDO5_EN
B1_EN
B2_EN
B3_EN
LDO_RTC TRACKING (nIO_TRACK)
LP3971 has a tracking function (nIO_TRACK). When en-
abled, LDO_RTC voltage will track LDO1 voltage within 200
mV down to 2.8V when LDO1 is enabled. This function can
be switched on/off by BPTR (8h’0E) register bit.
LDO4, LDO5 AND BUCK 2 ENABLE SELECTION
(LDO4_ESEL, LDO5_ESEL AND BUCK2_ESEL)
LDO4, 5 and BUCK2 power domain enable is possible to
change between SYS_EN and PWR_EN by register bits.
WAKE-UP FUNCTIONALITY (PWR_ON, nTEST_JIG,
SPARE AND EXT_WAKEUP)
Three input pins can be used to assert wakeup output for 10
ms for application processor notification to wakeup. SPARE
input can be programmed through I²C compatible interface
33
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