LP3971 Datasheet, PDF (19/42 Pages) National Semiconductor (TI) – POWER MANAGEMENT UNIT FOR ADVANCED APPLICATION PROCESSORS

I ²C Register Definitions (Continued)
Bit
Access
1
R
0
R
Name
WUPT
WUPS
TEST_JIG Pin Wake Up Status
0 = No wake up event
1 = Wake up event
SPARE Pin Wake Up Status
0 = No wake up event
1 = Wake up event
Description
SYSTEM CONTROL REGISTER 1 (SCR1) 8h’07
Bit
7
6
5
4
Designation
BPSEN
Reserved
SENDL
Reset Value
0
1
0
0
Note: Gray denotes EPROM programmable registers for default value.
SYSTEM CONTROL REGISTER 1 (SCR1) 8h’07 DEFINITIONS
3
FPWM3
0
2
FPWM2
0
1
FPWM1
0
0
ECEN
0
Bit Access
Name
Description
7
R/W
BPSEN Bypass System enable safety Lock. Prevents activation of PWR_EN when SYS_EN is low.
0 = PWR_EN “AND” with SYS_EN signal
1 = PWR_EN independent of SYS_EN
6
-
-
Reserved
5:4
R/W
SENDL Delay time for High Voltage Power Domains LDO2, LDO3, LDO4, Buck2, and Buck3 after
activation of SYS_EN. VCC_LDO1 has no delay.
Data Code
Delay mS
Notes
2h’0
0.0
Default for “B”
2h’1
0.5
2h’2
1.0
Default for “A”
2h’3
1.4
3
R/W
FPWM3 Buck 3 PWM/PFM Mode Select
0 - Auto Switch between PFM and PWM operation
1 - PWM Mode Only will not switch to PFM
2
R/W
FPWM2 Buck 2 PWM/PFM Mode Select
0 - Auto Switch between PFM and PWM operation
1 - PWM Mode Only will not switch to PFM
1
R/W
FPWM1 Buck 1 PWM/PFM Mode Select
0 - Auto Switch between PFM and PWM operation
1 - PWM Mode Only will not switch to PFM
0
R/W
ECEN
External Clock Select
0 = Internal Oscillator clock for Buck Converters
1 = External 13 MHz Oscillator clock for Buck Converters
19
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