LP3971 Datasheet, PDF (18/42 Pages) National Semiconductor (TI) – POWER MANAGEMENT UNIT FOR ADVANCED APPLICATION PROCESSORS

I ²C Register Definitions
I²C CONTROL REGISTERS
Register
Address
8h’02
8h’07
8h’0B
8h’0E
8h’10
8h’11
8h’12
8h’13
8h’20
8h’23
8h’24
8h’25
8h’29
8h’2A
8h’2B
8h’32
8h’33
8h’34
8h’38
8h’39
8h’3A
8h’3B
Register
Name
ISR
SCR1
BBCC
SCR2
BOVEN
BOVSR
LDOEN
LDOVS
VCC1
B1TV1
B1TV2
B1RC
B2TV1
B2TV2
B2RC
B3TV1
B3TV2
B3RC
BFR
L21VCR
L43VCR
L5VCR
Read/
Write
R
R/W
R/W
R/W
R/W
R
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Register Description
Interrupt Status Register A
System Control Register 1
Backup Battery Charger Control Register
System Control Register 2
Buck Output Voltage Enable Register
Buck Output Voltage Status Register
LDO Output Voltage Enable Register
LDO Output Voltage Status Register
Voltage Change Control Register 1
Buck 1 Target Voltage 1 Register
Buck 1 Target Voltage 2 Register
Buck 1 Ramp Control
Buck 2 Target Voltage 1 Register
Buck 2 Target Voltage 2 Register
Buck 2 Voltage Ramp Control
Buck 3 Target Voltage 1 Register
Buck 3 Target Voltage 2 Register
Buck 3 Voltage Ramp Control
Buck Function Register
LDO2 & 1 Voltage Control Registers
LDO4 & LDO3 Voltage Control Registers
LDO5 Voltage Control Registers
INTERRUPT STATUS REGISTER (ISR) 8h’02
Bit
Designation
Reset Value
7
T100
0
6
T125
0
5
GPI2
0
4
GPI1
0
3
WU3L
0
2
WUPS
0
1
WUPT
0
INTERRUPT STATUS REGISTER (ISR) 8h’02 DEFINITIONS
Bit
Access
7
-
6
R
5
R
4
R
3
R
2
R
Name
-
T125
GPI2
GPI1
WU3L
WUPS
Description
Reserved
Status bit for thermal warming PMIC T>125˚C
0 = PMIC Temp. <125˚C
1 = PMIC Temp. >125˚C
Status bit for the input read in from GPIO 2 when set as Input
0 = GPI2 Logic Low
1 = GPI2 Logic High
Status bit for the input read in from GPIO 1 when set as Input
0 = GPI1 Logic Low
1 = GPI1 Logic High
PWR_ON Pin Long Pulse Wake Up Status
0 = 1 No wake up event
1 = Long pulse wake up event
PWR_ON Pin Short Pulse Wake Up Status
0 = No wake up event
1 = Short pulse wake up event
0
WUPS
0
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