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| PC87366 Datasheet, PDF (39/240 Pages) National Semiconductor (TI) – 128-Pin LPC SuperI/O with System Hardware Monitoring, MIDI and Game Ports | |||
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2.0 Device Architecture and Configuration (Continued)
2.2.4 Standard Configuration Registers
SuperI/O Control and
Conï¬guration Registers
Logical Device Control and
Conï¬guration Registers -
one per Logical Device
(some are optional)
Index
07h
20h
21h
22h
23h
24h
25h
26h
27h
28h
2Ah
2Bh
2Ch
2Dh
2Eh
30h
60h
61h
62h
63h
70h
71h
74h
75h
F0h
F1h
F2h
Register Name
Logical Device Number
SuperI/O ID
SuperI/O Conï¬guration 1
SuperI/O Conï¬guration 2
SuperI/O Conï¬guration 3
SuperI/O Conï¬guration 4
SuperI/O Conï¬guration 5
SuperI/O Conï¬guration 6
SuperI/O Revision ID
SuperI/O Conï¬guration 8
SuperI/O Conï¬guration A
SuperI/O Conï¬guration B
SuperI/O Conï¬guration C
SuperI/O Conï¬guration D
Reserved exclusively for National use
Logical Device Control (Activate)
I/O Base Address Descriptor 0 Bits 15-8
I/O Base Address Descriptor 0 Bits 7-0
I/O Base Address Descriptor 1 Bits 15-8
I/O Base Address Descriptor 1 Bits 7-0
Interrupt Number and Wake-Up on IRQ Enable
IRQ Type Select
DMA Channel Select 0
DMA Channel Select 1
Device Speciï¬c Logical Device Conï¬guration 1
Device Speciï¬c Logical Device Conï¬guration 2
Device Speciï¬c Logical Device Conï¬guration 3
Figure 3. Conï¬guration Register Map
SuperI/O Control and Conï¬guration Registers
The SuperI/O Configuration registers at indexes 20h and 27h are mainly used for part identification, global power manage-
ment and the selection of pin multiplexing options. For details, see Section 2.8.
Logical Device Control and Conï¬guration Registers
A subset of these registers is implemented for each logical device. See functional block description in the following sections.
39
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