PC87366 Datasheet, PDF (158/240 Pages) National Semiconductor (TI) – 128-Pin LPC SuperI/O with System Hardware Monitoring, MIDI and Game Ports

9.0 Game Port (GMP) (Continued)
9.3 GAME PORT REGISTERS
The following abbreviations are used to indicate the Register Type:
q _{R/W = Read/Write}
q _{R = Read from a specific address returns the value of a specific register. Write to the same address is to a different}
register.
q _{W = Write}
q _{RO = Read Only}
q _{R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect.}
9.3.1 Game Port Register Map
The following table lists the Game Port registers. for the Game Port register bitmap, see Section 9.4.
Offset
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
Mnemonic
Register Name
GMPCTL Game Port Control
GMPLST Game Port Legacy Status
GMPXST Game Port Extended Status
GMPIEN Game Port Interrupt Enable
GMPAXL Game Device A X Position Low Byte
GMPAXH Game Device A X Position High Byte
GMPAYL Game Device A Y Position Low Byte
GMPAYH Game Device A Y Position High Byte
GMPBXL Game Device B X Position Low Byte
GMPBXH Game Device B X Position High Byte
GMPBYL Game Device B Y Position Low Byte
GMPBYH Game Device B Y Position High Byte
GMPEPOL Game Port Event Polarity
Type
R/W
RO
R/W1C
R/W
RO
RO
RO
RO
RO
RO
RO
RO
R/W
Section
9.3.2
9.3.3
9.3.4
9.3.5
9.3.6
9.3.7
9.3.8
9.3.9
9.3.10
9.3.11
9.3.12
9.3.13
9.3.14
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