PC87366 Datasheet, PDF (222/240 Pages) National Semiconductor (TI) – 128-Pin LPC SuperI/O with System Hardware Monitoring, MIDI and Game Ports

13.0 Legacy Functional Blocks (Continued)
13.5.3 SP2 Register Map for IR Functionality
.
Table 70. Bank 4 Register Map
Offset Mnemonic
Register Name
00h-01h
Reserved
02h
IRCR1 IR Control 1
03h LCR/BSR Line Control/Bank Select
04h - 07h
Reserved
Table 71. Bank 5 Register Map
Offset Mnemonic
Register Name
00h-02h
Reserved
03h LCR/BSR Line Control/Bank Select
04h
IRCR2 IR Control 2
05h - 07h Reserved
Table 72. Bank 6 Register Map
Offset Mnemonic
Register Name
00h
01h
02h
03h
04h-07h
IRCR3 IR Control 3
Reserved
SIR_PW SIR Pulse Width Control (≤ 115 Kbps)
LCR/BSR Line Control/Bank Select
Reserved
Table 73. Bank 7 Register Map
Offset
00h
01h
02h
03h
04h
05h
06h
07h
Mnemonic
Register Name
IRRXDC IR Receiver Demodulator Control
IRTXMC IR Transmitter Modulator Control
RCCFG CEIR Configuration
LCR/BSR Line Control/Bank Select
IRCFG1 IR Interface Configuration 1
Reserved
IRCFG3 IR Interface Configuration 3
IRCFG4 IR Interface Configuration 4
Type
R/W
R/W
Type
R/W
R/W
Type
R/W
R/W
R/W
Type
RO
RO
RO
R/W
R/W
R/W
R/W
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