PC87366 Datasheet, PDF (126/240 Pages) National Semiconductor (TI) – 128-Pin LPC SuperI/O with System Hardware Monitoring, MIDI and Game Ports

5.0 Fan Speed Monitor
5.1 OVERVIEW
This chapter describes a generic Fan Speed Monitor module. For the implementation used in this device, see the Device
Architecture and Configuration chapter.
The Fan Speed Monitor determines the fan’s speed by measuring the time between consecutive tachometer pulses, emitted
by the fan once or twice per revolution (depending on the fan type). It may provide the system with a current speed reading
and/or alert the system, by interrupt, whenever the speed drops below a programmable threshold. The Fan Speed Monitor
indicates whether the speed is just below the threshold or inefficiently low to consider the fan stopped.
Figure 15 shows the basic system configuration of the Fan Speed Monitor.
Fan
Tachometer Pulse
Filtering
Circuitry
(optional)
FANIN
Fan Speed
Monitor
Figure 15. Fan Speed Monitor - System Configuration
5.2 FUNCTIONAL DESCRIPTION
The fan emits a tachometer pulse every half or full revolution (depending on the fan type). These pulses are fed into the Fan
Speed Monitor through the FANIN input pin. Measuring the time between these pulses is the basis for speed monitoring.
NCBTP is defined as the Number of Clock-cycles Between consecutive Tachometer Pulses. For a known clock rate (f Hz)
and number of pulses per revolution (n=1,2), the Fan Speed is calculated according to the following relationship:
Fan Speed (in RPM) = 60 • _N-----_C-----_B----_T-^f---_P------_•----_n--
The Fan Speed Monitor consists of an 8-bit counter to measure the NCBTP and three 8-bit registers: Fan Monitor Speed
register (FMSPR), Fan Monitor Threshold register (FMTHR) and Fan Monitor Control and Status register (FMCSR). Figure
16 is a general block diagram of the Fan Speed Monitor.
The Up Counter and the FMSPR register are cleared to 0 while the Fan Speed Monitor is disabled (and in particular upon
system reset).
When the Fan Speed Monitor is enabled and there was no counter overflow, the counter runs (up-counts), clocked by the
selected clock rate. Starting from the second FANIN pulse (after activation) and upon every rising edge of FANIN when the
Over Threshold bit is 0, the FMSPR register is loaded with the contents of the counter, the counter is cleared to 0, and the
Speed Ready bit is set to 1.
Upon reading FMSPR, the Speed Ready bit of the FMCSR is cleared to 0.
The above operation continually repeats itself, providing the host with the current speed reading, as long as the FMSPR
register value is lower than the threshold.
Once the loaded FMSPR register value exceeds the threshold, the Over Threshold bit is set to 1. Interrupt is asserted if
enabled. The FMSPR register is not loaded with any new values when the Over Threshold bit is set. A new value is loaded
only after clearing the Over Threshold bit (by writing 1) and reading the FMSPR register. This guarantees that the same
NCBTP value that generated the interrupt remains available for the interrupt handler.
If the counter passes FFh, the Overflow bit is set to 1, the FMSPR register is cleared, and the interrupt is asserted, if enabled.
The Overflow bit is cleared to 0 when it is written with 1, after which speed measurement resumes.
The input buffer of the FANIN signal is a hysteresis buffer (Schmitt trigger). This signal passes through a digital filter when
the Filter Disable bit (bit 4 of the FMCSR register) is 0. The digital filter uses a 32 KHz clock to filter out any pulses shorter
than 750 µsec. This filter can be by-passed when setting bit 4 of the FMCSR register to 1.
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