PC87366 Datasheet, PDF (216/240 Pages) National Semiconductor (TI) – 128-Pin LPC SuperI/O with System Hardware Monitoring, MIDI and Game Ports

13.0 Legacy Functional Blocks (Continued)
13.4 UART FUNCTIONALITY (SP1 AND SP2)
13.4.1 General Description
Both SP1 and SP2 provide UART functionality. The generic SP1 and SP2 support serial data communication with remote
peripheral device or modem using a wired interface. The functional blocks can function as a standard 16450, 16550, or as
an Extended UART.
13.4.2 UART Mode Register Bank Overview
Four register banks, each containing eight registers, control UART operation. All registers use the same 8-byte address
space to indicate offsets 00h through 07h. The BSR register selects the active bank and is common to all banks. See Figure
47.
BANK 3
BANK 2
BANK 1
BANK 0
Offset 07h
Common
Register
Throughout
All Banks
Offset 06h
Offset 05h
Offset 04h
LCR/BSR
Offset 02h
Offset 01h
Offset 00h
16550 Banks
Figure 47. UART Mode Register Bank Architecture
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