PC87366 Datasheet, PDF (147/240 Pages) National Semiconductor (TI) – 128-Pin LPC SuperI/O with System Hardware Monitoring, MIDI and Game Ports

8.0 ACCESS.bus Interface (ACB) (Continued)
8.2.8 Slave Mode
A slave device waits in idle mode for a master to initiate a bus transaction. Whenever the ACB is enabled and it is not acting
as a master (the MASTER bit of the ACBST register is cleared), it acts as a slave device.
Once a Start Condition on the bus is detected, the device checks whether the address sent by the current master matches
either:
q _{The ADDR bit value of the ACBADDR register, if the SAEN bit =1, or}
q _{The general call address if the GCMEN bit of the ACBCTL1 register =1.}
This match is checked even when the MASTER bit is set. If a bus conflict (on SDA or SCL) is detected, the BER bit of the
ACBST register is set, the MASTER bit is cleared and the device continues to search the received message for a match.
If an address match or a global match is detected:
1. The device asserts its SDA pin during the acknowledge cycle.
2. The MATCH bit of the ACBCST register and the NMATCH bit of the ACBST register are set. If the XMIT bit of the ACBST
register is set (slave transmit mode), the SDAST bit of the ACBST register is set to indicate that the buffer is empty.
3. If the INTEN bit of the ACBCTL1 register is set, an interrupt is generated the NMINTE bit is also set.
4. The software then reads the XMIT bit of the ACBST register to identify the direction requested by the master device. It
clears the NMATCH bit of the ACBST Registe so future byte transfers are identified as data bytes.
Slave Receive and Transmit
Slave receive and transmit are performed after a match is detected and the data transfer direction is identified. After a byte
transfer, the ACB extends the acknowledge clock until the software reads or writes the ACBSDA register. The receive and
transmit sequences are identical to those used in the master routine.
Slave Bus Stall
When operating as a slave, the device stalls the ACCESS.bus by extending the first clock cycle of a transaction in the fol-
lowing cases:
q _{SDAST bit of the ACBST register is set.}
q _{NMATCH bit of the ACBST register and NMINTE bit of the ACBCTL1 register are set.}
Slave Error Detection
The ACB detects illegal Start and Stop Conditions on the ACCESS.bus (i.e., a Start or Stop Condition within the data transfer
or the acknowledge cycle). When this occurs, the BER bit is set and MATCH and GMATCH are cleared, setting the ACB as
an unaddressed slave.
8.2.9 Configuration
SDA and SCL Signals
The SDA and SCL are open-drain signals. The device permits the user to define whether to enable or disable the internal
pull-up of each of these signals.
ACB Clock Frequency
The ACB permits the user to set the clock frequency for the ACCESS.bus clock. The clock is set by the the SCLFRQ field
of the ACBCTL2 register, which determines the SCL clock period used by the device. This clock low period may be extended
by stall periods initiated by the ACB or by another ACCESS.bus device. In case of a conflict with another bus master, a short-
er clock high period may be forced by the other bus master until the conflict is resolved.
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