LMH2190 Datasheet, PDF (3/24 Pages) National Semiconductor (TI) – Quad Channel 27 MHz Clock Tree Driver with I2C Interface

Symbol
Parameter
Condition
Jitter_RMS Additive RMS period Jitter
BW = 100 Hz to 1 MHz CLK1
CLK2
CLK3
CLK4
Phase
Noise
CLK1 Additive Phase Noise with f = 100 Hz
all Outputs toggling
f = 1 kHz
f = 10 kHz
f = 100 kHz
f = 1 MHz
CLK2 Additive Phase Noise with f = 100 Hz
all Outputs toggling
f = 1 kHz
f = 10 kHz
f = 100 kHz
f = 1 MHz
CLK3 Additive Phase Noise with f = 100 Hz
all Outputs toggling
f = 1 kHz
f = 10 kHz
f = 100 kHz
f = 1 MHz
CLK4 Additive Phase Noise with f = 100 Hz
all Outputs toggling
f = 1 kHz
f = 10 kHz
f = 100 kHz
f = 1 MHz
V_OH
CLK1/2/3/4 Output Voltage High CLK1/2/3/4 = -2 mA
Level
V_OL
CLK1/2/3/4 Output Voltage Low CLK1/2/3/4 = 2 mA
Level
System Clock Input (SCLK_IN)
V_IH
SCLK_IN Input Voltage High DC Mode
Level
AC Mode
V_IL
SCLK_IN Input Voltage Low
DC Mode
Level
AC Mode
I_IH
SCLK_IN Input Current High SCLK_IN = 1.8V, Clock path disabled
Level
I_IL
SCLK_IN Input Current Low
SCLK_IN = V_SS, Clock path disabled
Level
C_IN
V_BIAS
R_IN
Input Capacitance (Note 7)
DC Bias Voltage
Input Resistance
AC Mode
AC Mode, Clock path enabled.
Min
(Note 6)
Typ
(Note 5)
100
240
330
400
-130
-144
-152
-158
-165
-128
-139
-146
-151
-153
-127
-138
-144
-148
-150
-125
-135
-142
-147
-148
Max
(Note 6)
1.6
0.2
0.65 x
V_OUT
1.2
0
0
-0.1
0
0
7.5
0.805
21
2.0
1.8
0.35 x
V_OUT
0.6
0.1
10
30
Units
fs
dBc/Hz
V
V
V
µA
µA
pF
V
kΩ
3
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