LMH2190 Datasheet, PDF (12/24 Pages) National Semiconductor (TI) – Quad Channel 27 MHz Clock Tree Driver with I2C Interface

PHASE NOISE
An important specification for oscillators and clock buffers is
phase noise. It determines the timing and thus accuracy of
various peripheral devices in a cell phone such as Bluetooth,
WLAN and DVB-H.
Phase noise is expressed in the frequency domain and is
usually specified at a number of offset frequencies from the
carrier frequency. The phase noise of the oscillator and the
LMH2190 together determine the phase noise of the clock
that is distributed to the peripheral devices. Therefore an ad-
ditive phase noise is specified for the LMH2190 rather than
its total output phase noise since that depends on the TCXO
connected to the LMH2190.
Knowing the TCXO phase noise and the additive phase noise
of the LMH2190, the total phase noise to the peripheral can
be calculated:
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Where, PN is the total phase noise at the output of the
LMH2190, PN_TCXO is the TCXO’s phase noise and
add.PN_LMH2190 is the additive phase noise of the
LMH2190, all in dBc/Hz.
CLOCK TREE DRIVER
The clock tree driver consists of one input that drives 4 outputs
(Figure 6). It is supplied by the highly accurate 1.8V LDO. In
default configuration the outputs are switched on when the
clock request inputs are high. The input as well as the output
can be configured in several ways though I²C programming.
Clock Tree Driver Input
The source clock input (SCLK_IN) is the input for the clock
tree driver. It can be configured to DC or AC coupled mode.
In shutdown mode, the input stage is completely switched off
to prevent unnecessary power consumption when the source
clock is still present.
In the DC coupled mode, the clock input may range from 32
kHz to 27 MHz. DC coupling mode requires that the input is
a square wave.
In AC mode an external capacitor needs to be connected in
series with the clock source and the SCLK_IN pin to block
external DC. Internally, a DC bias network centers it at about
V_OUT/2. This enables the use of a sine wave clock source with
a amplitude between 0.8 V_PP and 1.8 V_PP. The bias voltage
is enabled only when the clock request output is activated in
order to eliminate the DC power. In the AC coupled mode, the
clock input may range from 13 MHz up to 27 MHz. It is as-
sumed to be a sine wave. Signals with sharp edges, such as
square wave signals, should be prevented as the DC control
loop will not be able to maintain its internal DC level.
Clock Tree Driver Outputs
The LMH2190's clock tree driver outputs have many modes
of operation to reduce power consumption and minimize EMI.
The output drive strength of the LMH2190 can be selected in
4 steps based on the load capacitance it needs to drive. The
configuration can be done via the I²C interface.
There are two dedicated methods for reducing EMI that can
be selected through the I²C interface. As shown in Figure 7
the first method (default) skews all of the clock edges individ-
ually, so that the EMI generated by the switching is spread
out over time. The second method inverts two of the outputs
and also skews one pair from the other.
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FIGURE 6. Clock Tree Driver
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