LMH2190 Datasheet, PDF (17/24 Pages) National Semiconductor (TI) – Quad Channel 27 MHz Clock Tree Driver with I2C Interface

I²C Timing
The timing of the SDA and SCL signals is depicted in Figure 17 and the parameters are given in Table 1.
FIGURE 17. I²C Timing Diagram
30083825
Symbol
f_SCL
1
2
3
4
5
5
6
7
8
9
10
C_b
TABLE 1. I²C Timing
Parameter
Limit
Min
Max
Clock Frequency
400
Hold Time (repeated) START Condition
0.6
Clock Low Time
1.3
Clock High Time
600
Setup Time for a Repeated START Condition
600
Data Hold Time (Output direction, delay generated by
300
900
LMH2190)
Data Hold Time (Input direction, delay generated by the
Master)
0
900
Data Setup Time
100
Rise Time of SDA and SCL
Fall Time of SDA and SCL
Set-up Time for STOP condition
20+0.1 C_b
300
10+0.1 C_b
300
600
Bus Free Time between a STOP and a START
Condition
1.3
Capacitive Load for Each Bus Line
10
200
Units
kHz
µs
ns
ns
ns
µs
ns
ns
ns
ns
ns
µs
pF
17
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