LMH2190 Datasheet, PDF (13/24 Pages) National Semiconductor (TI) – Quad Channel 27 MHz Clock Tree Driver with I2C Interface

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(a) Outputs with Skew only
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(b) Outputs with Skew and Inversion
FIGURE 7. Clock Outputs Timing
CLOCK REQUEST LOGIC
The clock request logic enables an independent control of the
clock tree driver outputs (CLK1 to CLK4) as well as an overall
source clock request (SCLK_REQ) and LDO enabling. Since
the clock request logic always needs to be active, it is supplied
by either the output of the LDO (V_OUT) or by the external EN-
ABLE. Further details about the selection between V_OUT and
ENABLE can be found in the LOW DROPOUT REGULA-
TOR section later in the datasheet.
Clock Request Inputs
A clock request input is provided for each clock output (Figure
8). This allows the peripheral device to control the LMH2190
when it wants to receive a clock. In case the peripheral device
does not have clock request functionality, the CLKx_REQ can
be wired to a logic high level to enable the clock output (in
default register setting). Alternatively, it can be controlled
through I²C. The CLKx_REQ input can be configured to be
active high or active low. When the LDO is off, the clock re-
quest logic still need to be powered such that it can turn on
the LDO. This is why the ENABLE input is used to power the
Clock Request Logic in case the LDO is off. Although the
CLK_REQ logic is supplied with 1.8V LDO voltage (or EN-
ABLE), the CLKx_REQ input can tolerate voltages up to
V_BAT.
To prevent glitches on CLK outputs, enabling of the outputs
is done synchronously. A latch is used to ensure that the CLK
outputs will be enabled on the falling edge of the source clock
input (SCLK_IN).
FIGURE 8. Clock Request Input
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System Clock Request Output
In the typical mode of operation, the clock request output will
be enabled if one of the 4 CLK_REQ inputs is high (Figure
9). However, this can be overridden via the I²C interface which
has a register bit that forces the output to be enabled, inde-
pendent of the CLK_REQ input. The polarity of the output can
be controlled via I²C (CLK_REQ Output Polarity) along with
whether the output is configured as push/pull, open drain or
open source.
For the open drain case, there needs to be an external resistor
that pulls the SCLK_REQ to a high level. This high level may
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