LMH2190 Datasheet, PDF (2/24 Pages) National Semiconductor (TI) – Quad Channel 27 MHz Clock Tree Driver with I2C Interface

Absolute Maximum Ratings (Note 1)
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please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
V_BAT - V_SS
LVCMOS port IO voltage
Current on CLKx pins
ESD Tolerance (Note 2)
Human Body Model
Machine Model
Storage Temperature Range
Junction Temperature (Note 3)
Maximum Lead Temperature
(Soldering,10 sec)
-0.3V to 6V
-0.3V to (V_OUT + 0.3V)
+/- 65 mA
2000V
200V
−65°C to 150°C
150°C
230°C
Operating Ratings (Note 1)
Supply Voltage (V_BAT - V_SS)
V_ENABLE
Input Clock, SCLK_IN
DC Mode
AC Mode
Duty Cycle
Temperature Range
Package Thermal Resistance θ_JA
(Note 3)
2.5V to 5.5V
0 to 2V
32 kHz to 27 MHz
13 MHz to 27 MHz
45% to 55%
-20°C to +85°C
113.6°C/W
3.5 V DC and AC Electrical Characteristics (Note 4, Note 11)
Unless otherwise specified, all limits are guaranteed at T_A = 25°C, V_BAT = 3.5V, f_{SCLK_IN} = 26 MHz, C_OUT = 2.2 µF, V_{DD_IO} = 1.8V
(See Block Diagram and (Note 9)), I_OUT = 1 mA, Registers are in default setting. Boldface limits apply at the temperature extremes.
Symbol
Parameter
Condition
Min
Typ
Max
(Note 6) (Note 5) (Note 6)
Units
Supply Current (Note 8)
I_DD
Active Supply Current
Clock outputs toggling at 26 MHz
without external capacitors on
CLK1/2/3/4, LDO is ON, I_OUT = 0 mA
Shutdown Supply Current
In Shutdown. No clocks toggling. LDO is
OFF
In Shutdown. Input CLK toggling, no
Clock outputs toggling. LDO is OFF
3
mA
0.1
1
μA
0.1
1
I_DDQ
Quiescent Supply Current
I_DDEN
Current to Enable pin
No Clock outputs toggling. LDO is ON,
I_OUT = 0 mA
No Clock outputs toggling, LDO is ON,
I_OUT = 10 mA
I²C port is operational
I²C port is idle
36
60
μA
50
80
300
μA
0.1
C_PD
Power Dissipation Capacitance Defined with respect to V_OUT = 1.8V
per CLK output, (Note 7)
15.7
17.5
pF
Clock Outputs (CLK1/2/3/4)
tp_LH
Propagation Delay SCLK_IN to 50% to 50%
CLK1 - Low to High, Figure 1
(Note 7)
6.5
10
ns
tp_HL
Propagation Delay SCLK_IN to 50% to 50%
CLK1 - High to Low, Figure 1
(Note 7)
7.5
11
ns
t_SKEW
Skew Between Outputs (Either
Edge), Figure 1, (Note 7)
CLK1 to CLK2, 50% to 50%
CLK2 to CLK3 and CLK3 to CLK4,
50% to 50%
3
6
8.5
ns
1
3.5
7.3
t_RISE
t_FALL
Rise Time, Figure 3,
(Note 7, Note 13)
C_L = 10 pF to 50 pF, 20% to 80%
Fall Time, Figure 3, (Note 7, Note C_L = 10 pF to 50 pF, 80% to 20%
13)
3
6
ns
2.5
5
CLK_DC Output Clock Duty Cycle,
Figure 3, (Note 7)
C_L = 10 pF to 50 pF
42
50
58
%
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