LMH2190 Datasheet, PDF (16/24 Pages) National Semiconductor (TI) – Quad Channel 27 MHz Clock Tree Driver with I2C Interface

edge clock pulse. The receiver must pull down the SDA line
during the 9th clock pulse, signifying an acknowledge. A re-
ceiver which has been addressed must generate an acknowl-
edge after each byte has been received.
After the START condition, the I²C master sends a chip ad-
dress (Figure 14). This address is seven bits long followed by
an eight bit which is a data direction bit (R/W). For the eighth
bit, a “0” indicates a WRITE and a “1” indicates a READ. The
second byte selects the register to which the data will be writ-
ten. The third byte contains data to write to the selected
register.
Register changes take effect at the SCL rising edge during
the last ACK from slave. An example of a WRITE cycle is
given in Figure 15. When a READ function is to be accom-
plished, a WRITE function must precede the READ function,
as shown in the Read Cycle waveform (Figure 16).
FIGURE 14. I²C Chip Address
30083820
FIGURE 15. Example I²C Write Cycle
30083823
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FIGURE 16. Example I²C Read Cycle
16
30083824