LMH2190 Datasheet, PDF (15/24 Pages) National Semiconductor (TI) – Quad Channel 27 MHz Clock Tree Driver with I2C Interface

FIGURE 11. Linear Regulator Block Diagram
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The LDO contains thermal overheating detection. If it does
overheat, the LMH2190 (except the register logic) will shut-
down and sets a status bit in the I²C status register.
The LDO can be configured to be always ON for the case
when it needs to supply power to the TCXO even when the
LMH2190 is not requesting any clocks to be distributed.
It is possible to use an external 1.8V supply connected to
V_OUT and shut off the internal LDO, although it is highly rec-
ommended to use the internally generated 1.8V. If an external
supply is used, care should be taken during startup as the
default configuration is for the internal LDO to be enabled. In
this case, there could be contention between the two supplies
which could cause excessive current flow.
I²C CONTROL LOGIC
The LMH2190 can be controlled by a I²C host device. The
I²C address of the LMH2190 is 38h. It can configure the reg-
isters inside the LMH2190 to change the default configura-
tion. The I²C communication is based on a READ/WRITE
structure, following the I²C transmission protocol. According
to the I²C specification one set of pull-up resistors needs to
be present on the I²C bus.
Some of the features are for instance setting the polarity of
the clock request inputs and outputs and setting the drive
strength of the clock outputs. It also allows direct control of
the clock request signals and the LDO via the I²C. The I²C
interface is powered by the ENABLE, while the control logic
and registers are powered by the V_BAT.
I²C Data Validity
The data on SDA line must be stable during the HIGH period
of the clock signal (SCL). In other words, the state of the data
line should only change when SCL is LOW (Figure 12).
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FIGURE 12. I²C Signals: Data Validity
I²C Start and Stop Condition
START and STOP bits classify the beginning and the end of
the I²C session. START condition is defined as SDA signal
transitioning from HIGH to LOW while SCL line is HIGH (Fig-
ure 13). STOP condition is defined as the SDA transitioning
from LOW to HIGH while SCL is HIGH. The I²C master always
generates START and STOP bits. The I²C bus is considered
to be busy after START condition and free after STOP con-
dition. During data transmission, I²C master can generate
repeated START conditions. First START and repeated
START conditions are equivalent, function-wise.
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FIGURE 13. I²C Start and Stop Conditions
Transferring Data
Every frame on the SDA line must be eight bits long, with the
most significant bit (MSB) being transferred first. Each byte of
data has to be followed by an acknowledge bit. The acknowl-
edge related clock pulse is generated by the master. The
transmitter releases the SDA line (HIGH) during the acknowl-
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