MC68HC901 Datasheet, PDF (53/73 Pages) Motorola, Inc – Multi-Function Peripheral

Universal Synchronous/Asynchronous Receiver-Transmitter
interrupts for this channel. Once the transfer is complete, interrupt pending register A is
read. Any pending receiver or transmitter error indicates an error in the data transfer.
RR is asserted when the buffer full bit is set in the RSR unless a parity error or frame error
is detected by the receiver. TR is asserted when the buffer empty bit is set in the TSR unless
a break is currently being transmitted.
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MC68HC901 USER’S MANUAL
MOTOROLA