MC68HC901 Datasheet, PDF(37/73 Page) Motorola, Inc

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

MC68HC901 Datasheet, PDF (37/73 Pages) Motorola, Inc – Multi-Function Peripheral

◁

General Purpose Input/Output Port

the active edge register will cause the associated input to generate an interrupt on the one-

to-zero transition. Writing a one to the edge bit will produce an interrupt on the zero-to-one

transition of the corresponding line. When the processor sets a bit, interrupts will be

generated on the rising edge of the associated input signal. When the processor clears a bit,

interrupts will be generated on the falling edge of the associated input signal.

AER REGISTER

BIT

FIELD

GPIP7

RESET

ADDR

GPIP6

GPIP5

GPIP4

GPIP3

$03

GPIP2

GPIP1

GPIP0

GPIP7-GPIP0 â General Purpose I/O Port

0 = Interrupts will be generated on the falling edge of the associated input signal.

1 = Interrupts will be generated on the rising edge of the associated input signal.

NOTE

The inputs to the exclusive-OR of the transition detector are the

edge bit and the input buffer. As a result, writing the AER may

cause an interrupt-producing transition, depending upon the

state of the input. So, the AER should be configured before

enabling interrupts via the interrupt enable registers (IERA and

IERB). Also, changing the edge bit while interrupts are enabled

may cause an interrupt on the corresponding channel.

5.1.3 Data Direction Register (DDR)

The data direction register (DDR) allows the programmer to define I0 through I7 as inputs

or outputs by writing the corresponding bit. When a bit of the data direction register is written

as a zero, the corresponding interrupt I/O pin will be a high-impedance input. Writing a one

to any bit of the data direction register will cause the corresponding pin to be configured as

a push-pull output.

DDR REGISTER

BIT