MC68HC901 Datasheet, PDF (33/73 Pages) Motorola, Inc – Multi-Function Peripheral

Interrupt Structure
4.3.4 Interrupt In-Service Registers (ISRA, ISRB)
These registers indicate whether interrupt processing is in progress for a certain channel. A
bit is set whenever an interrupt vector number is passed for a interrupt channel during an
IACK cycle and the S bit of the vector register is a one. The bit is cleared whenever interrupt
service is complete for an associated interrupt channel, the S bit of the vector register is
cleared, or the processor writes a zero to the bit.
ISRA REGISTER
BIT
7
FIELD
GPIP7
RESET
0
ADDR
6
GPIP6
0
5
TIMER A
0
4
3
RCV
BUFFER
FULL
RCV
ERROR
0
0
$0F
2
XMIT
BUFFER
EMPTY
0
1
XMIT
ERROR
0
0
TIMER B
0
GPIP7-GPIP6 — General Purpose Interrupt Servicing
1 = In-service.
0 = No service in progress.
Timer A — Timer A Interrupt Servicing
1 = In-service.
0 = No service in progress.
Receiver Buffer Full — Receiver Buffer Full Interrupt Servicing
1 = In-service.
0 = No service in progress.
Receiver Error — Receiver Buffer Full Interrupt Servicing
1 = In-service.
0 = No service in progress.
Transmitter Buffer Empty — Transmitter Buffer Interrupt Servicing
1 = In-service.
0 = No service in progress.
Transmitter Error — Transmitter Error Interrupt Servicing
1 = In-service.
0 = No service in progress.
Timer B — Timer B Interrupt Servicing
1 = In-service.
0 = No service in progress.
4-10
MC68HC901 USER’S MANUAL
MOTOROLA