MC68HC901 Datasheet, PDF (29/73 Pages) Motorola, Inc – Multi-Function Peripheral

Interrupt Structure
4.3.2 Interrupt Pending Registers (IPRA, IPRB)
When an interrupt is received on an enabled channel, the corresponding interrupt pending
bit is set in interrupt pending register A or B (IPRA or IPRB). In a vectored interrupt scheme,
this bit will be cleared when the processor acknowledges the interrupting channel and the
MFP responds with a vector number. In a polled interrupt system, the interrupt pending
registers must be read to determine the interrupting channel, and then the interrupt pending
bit is cleared by the interrupt handling routine without performing an interrupt acknowledge
sequence.
IPRA REGISTER
BIT
7
FIELD
GPIP7
RESET
0
ADDR
6
GPIP6
0
5
TIMER A
0
4
3
RCV
BUFFER
FULL
RCV
ERROR
0
0
$0B
2
XMIT
BUFFER
EMPTY
0
1
XMIT
ERROR
0
0
TIMER B
0
GPIP7-GPIP6 — General Purpose Interrupt Pending
1 = Pending.
0 = Cleared.
Timer A — Timer A Interrupt Pending
1 = Pending.
0 = Cleared.
Receiver Buffer Full — Receiver Buffer Full Interrupt Pending
1 = Pending.
0 = Cleared.
Receiver Error — Receiver Buffer Full Interrupt Pending
1 = Pending.
0 = Cleared.
Transmitter Buffer Empty — Transmitter Buffer Interrupt Pending
1 = Pending.
0 = Cleared.
Transmitter Error — Transmitter Error Interrupt Pending
1 = Pending.
0 = Cleared.
Timer B — Timer B Interrupt Pending
1 = Pending.
0 = Cleared.
4-6
MC68HC901 USER’S MANUAL
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