MC68HC901 Datasheet, PDF (21/73 Pages) Motorola, Inc – Multi-Function Peripheral

Bus Operation
CLK
R/W
CS
DS
RS1 - RS5
D0 - D7
DTACK
Figure 3-1. Read Cycle Timing Diagram
3.1.2 Write Cycle
To write a register, CS and DS mus^Ft^IGb^URe^E a^{- R}s_MEs_CA6De_8Cr_Ht^YCe^C90Ld_1E,_UTMa^IM/n^IANd_DG ^DR^IA/^GW^RAMmust be low. The MFP will
decode the address bus to determine which register is selected. Then the register will be
loaded with the contents of the data bus on the next valid falling edge of CLK, and DTACK
will be asserted. When the processor recognizes DTACK, it will negate DS. The write cycle
is terminated when either CS or DS is negated. The MFP will drive DTACK high and place
it in the high-impedance state. The timing for a write cycle is shown in Figure 3-2. Refer to
Section 8.7 AC Electrical Characteristics for actual timing numbers.
CLK
R/W
CS
DS
RS1 - RS5
D0 - D7
DTACK
Figure 3-2. Write Cycle Timing Diagram
3.2 INTERRUPT ACKNOWLEDGE OPERATION
The MFP has 16 interrupt sources^F:^IGe^Ui^Rg^Eh^- t^WMi^Rn_CIT6t^E8e_HCr_CYn_9C0a^L1EUl ^TMa^IM/n_AINd_DG ^De^IAig^Gh^RAt^Mexternal. When an interrupt
request is pending, the MFP will assert IRQ. In a vectored interrupt scheme, the processor
will acknowledge the interrupt request by performing an interrupt acknowledge cycle. IACK
and DS will be asserted. The MFP responds to the IACK signal by placing a vector number
on the data bus. This vector number corresponds to the particular interrupt channel
requesting service. The format of this vector number is further discussed in Section 4.1.2
Interrupt Vector Number.
3-2
MC68HC901 USER’S MANUAL
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