MC68HC901 Datasheet, PDF (31/73 Pages) Motorola, Inc – Multi-Function Peripheral

Interrupt Structure
4.3.3 Interrupt Mask Registers (IMRA, IMRB)
Interrupts are masked for a channel by clearing the appropriate bit in interrupt mask register
A or B (IMRA or IMRB). Even though an enabled channel is masked, the channel will
recognize subsequent interrupts and set its interrupt pending bit. However, the channel is
prevented from requesting interrupt service (IRQ to the processor) as long as the mask bit
for that channel is cleared. If a channel is requesting interrupt service at the time that its
corresponding bit in IMRA or IMRB is cleared, the request will cease, and IRQ will be
negated unless another channel is requesting interrupt service. Later, when the mask bit is
set, any pending interrupt on the channel will be processed according to the channel's
assigned priority. IMRA and IMRB may be read at any time. Figure 4-2 provides a
conceptual circuit of an MFP interrupt channel.
IMRA REGISTER
BIT
7
FIELD
GPIP7
RESET
0
ADDR
6
GPIP6
0
5
TIMER A
0
4
3
RCV
BUFFER
FULL
RCV
ERROR
0
0
$13
2
XMIT
BUFFER
EMPTY
0
1
XMIT
ERROR
0
0
TIMER B
0
GPIP7-GPIP6 — General Purpose Interrupt Mask
1 = Unmask.
0 = Mask.
Timer A — Timer A Interrupt Mask
1 = Unmask.
0 = Mask.
Receiver Buffer Full — Receiver Buffer Full Interrupt Mask
1 = Unmask.
0 = Mask.
Receiver Error — Receiver Buffer Full Interrupt Mask
1 = Unmask.
0 = Mask.
Transmitter Buffer Empty — Transmitter Buffer Interrupt Mask
1 = Unmask.
0 = Mask.
Transmitter Error — Transmitter Error Interrupt Mask
1 = Unmask.
0 = Mask.
4-8
MC68HC901 USER’S MANUAL
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