MC68HC901 Datasheet, PDF (45/73 Pages) Motorola, Inc – Multi-Function Peripheral

Universal Synchronous/Asynchronous Receiver-Transmitter
7.1.1 Asynchronous Format
Variable character length and start/stop bit configurations are available under software
control for asynchronous operation. The user can choose a character length from five to
eight bits and a stop bit length of one, one and one-half, or two bits. The user can also select
odd, even, or no parity.
In the asynchronous format, start bit detection is always enabled. New data is not shifted
into the receive shift register until a zero bit is received. When the divide-by-16 clock mode
is selected, the false start bit logic is also active. Any transition must be stable for three
positive receive clock edges to be considered valid. For a start bit to be good, a valid zero-
to-one transition must not occur for eight positive receiver clock transitions after the initial
one-to-zero transition. After a valid start bit has been detected, the data is checked
continuously for valid transitions. When a valid transition is detected, an internal counter is
forced to state zero, and no further transition checking is initiated until state four. At state
eight, the “previous state” of the transition checking logic is clocked into the receiver. As a
result of this re-synchronization logic, it is possible to run with asynchronous clocks without
start and stop bits if there are sufficient valid transitions in the data streams.
7.1.2 Synchronous Format
When the synchronous character format is selected, the 8-bit synchronous character loaded
into the synchronous character register (SCR) is compared to received serial data until a
match is found. Once synchronization is established, incoming data is clocked into the
receiver. The synchronous word will be continuously transmitted during an underrun
condition. All synchronous characters can be optionally stripped from the receive buffer (i.e.,
taken out of the data stream and thrown away) by clearing the appropriate bit in the receive
status register (RSR).
SCR REGISTER
BIT
7
6
5
4
3
2
1
0
FIELD
D7
D6
D5
D4
D3
D2
D1
D0
RESET
0
0
0
0
0
0
0
0
ADDR
$27
D7-D0 — Data
0 = Cleared.
1 = Set.
The synchronous character should be written after the character length is selected, since
unused bits in the synchronous character register are zeroed out. When parity is enabled,
synchronous word length is the character length plus one. The MFP will compute and
append the parity bit for the synchronous character.
7-2
MC68HC901 USER’S MANUAL
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