MC68HC901 Datasheet, PDF (35/73 Pages) Motorola, Inc – Multi-Function Peripheral

Interrupt Structure
the MFP is placed in the software end-of-interrupt mode, and when the S bit is a zero, all
channels operate in the automatic end-of-interrupt mode.
4.4.2 Automatic End-Of-Interrupt Mode
When an interrupt vector is passed to the processor during an interrupt acknowledge cycle,
the corresponding channel's interrupt pending bit is cleared. In the automatic end-of-
interrupt mode, no further history of the interrupt remains in the MFP. The in-service bits of
the interrupt in-service registers (ISRA and ISRB) are forced low. Subsequent interrupts,
which are received on any MFP channel will generate an interrupt request to the processor
even if the current interrupt's service routine has not been completed.
4.4.3 Software End-Of-Interrupt Mode
In the software end-of-interrupt mode, the channel's associated interrupt pending bit is
cleared. In addition, the channel's in-service bit of in-service register A or B is set when its
vector number is passed to the processor during the interrupt acknowledge cycle. A higher
priority channel may subsequently request interrupt service and be acknowledged, but as
long as the channel's in-service bit is set, no lower priority channel may request interrupt
service nor pass its vector during an interrupt acknowledge sequence.
While only higher priority channels may request interrupt service, any channel can receive
an interrupt and set its interrupt pending bit. Even the channel with its in-service bit is set
can receive a second interrupt. However, no interrupt service request is made until its
in-service bit is cleared.
The in-service bit for a particular channel can be cleared by writing a zero to its
corresponding bit in ISRA or ISRB and ones to all other bit positions. Since bits in the
in-service registers can only be cleared in software and not set, writing ones to the registers
does not alter their contents. ISRA and ISRB may be read at any time.
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MC68HC901 USER’S MANUAL
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